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MSPM0 G系列 80-MHz Microcontrollers用户手册
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MSPM0GSeries 80-MHz Microcontrollers用户手册 本手册介绍了 MSPM0G系列器件的模块和外设。 各说明 呈现一般意义上的模块或外围设备。 并非所有模块或外设的所有特性和功能 存在于所有设备上。 此外，模块或外设的具体实现可能有所不同 不同的设备。 引脚功能、内部信号连接和操作参数因器件而异 设备。 有关这些详细信息，请参阅特定于器件的数据表。
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Read This First......................................................................................................................................................................... 11
About This Manual..................................................................................................................................................................11
Notational Conventions.......................................................................................................................................................... 11
Glossary................................................................................................................................................................................. 11
Support Resources.................................................................................................................................................................11
Trademarks.............................................................................................................................................................................11
1 Architecture...........................................................................................................................................................................13
1.1 Architecture Overview...................................................................................................................................................... 14
1.2 Bus Organization..............................................................................................................................................................14
1.3 Platform Memory Map......................................................................................................................................................16
1.3.1 Code Region..............................................................................................................................................................16
1.3.2 SRAM Region............................................................................................................................................................16
1.3.3 Peripheral Region......................................................................................................................................................18
1.3.4 Subsystem Region.................................................................................................................................................... 18
1.3.5 System PPB Region.................................................................................................................................................. 18
1.4 Boot Configuration........................................................................................................................................................... 18
1.4.1 Configuration Memory (NONMAIN)...........................................................................................................................19
1.4.2 Boot Configuration Routine (BCR)............................................................................................................................ 20
1.4.3 Bootstrap Loader (BSL).............................................................................................................................................26
1.5 NONMAIN Registers........................................................................................................................................................ 29
1.6 Factory Constants............................................................................................................................................................ 57
1.6.1 FACTORYREGION Registers................................................................................................................................... 58
2 PMCU..................................................................................................................................................................................... 93
2.1 PMCU Overview...............................................................................................................................................................94
2.1.1 Power Domains......................................................................................................................................................... 95
2.1.2 Operating Modes....................................................................................................................................................... 95
2.2 Power Management (PMU)..............................................................................................................................................99
2.2.1 Power Supply.......................................................................................................................................................... 100
2.2.2 Core Regulator........................................................................................................................................................ 100
2.2.3 Supply Supervisors..................................................................................................................................................100
2.2.4 Bandgap Reference.................................................................................................................................................102
2.2.5 Temperature Sensor................................................................................................................................................ 102
2.2.6 VBOOST for Analog Muxes.....................................................................................................................................103
2.2.7 Peripheral Power Enable Control............................................................................................................................ 105
2.3 Clock Module (CKM)...................................................................................................................................................... 106
2.3.1 Oscillators................................................................................................................................................................106
2.3.2 Clocks...................................................................................................................................................................... 118
2.3.3 Clock Tree............................................................................................................................................................... 127
2.3.4 Clock Monitors.........................................................................................................................................................129
2.3.5 Frequency Clock Counter (FCC) ............................................................................................................................ 132
2.4 System Controller (SYSCTL)......................................................................................................................................... 135
2.4.1 Resets and Device Initialization...............................................................................................................................135
2.4.2 Operating Mode Selection....................................................................................................................................... 143
2.4.3 Asynchronous Fast Clock Requests........................................................................................................................144
2.4.4 SRAM Write Protection............................................................................................................................................146
2.4.5 Flash Wait States.....................................................................................................................................................146
2.4.6 Flash Bank Address Swap...................................................................................................................................... 147
2.4.7 Shutdown Mode Handling....................................................................................................................................... 147
2.4.8 Configuration Lockout..............................................................................................................................................147
2.4.9 System Status......................................................................................................................................................... 148
Table of Contents
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2.4.10 Error Handling....................................................................................................................................................... 148
2.4.11 SYSCTL Events.....................................................................................................................................................150
2.5 Quick Start Reference....................................................................................................................................................151
2.5.1 Default Device Configuration...................................................................................................................................151
2.5.2 Leveraging MFCLK..................................................................................................................................................152
2.5.3 Optimizing Power Consumption in STOP Mode......................................................................................................152
2.5.4 Optimizing Power Consumption in STANDBY Mode...............................................................................................152
2.5.5 Increasing MCLK and ULPCLK Precision............................................................................................................... 153
2.5.6 Configuring MCLK for Maximum Speed.................................................................................................................. 153
2.5.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes................................................................... 153
2.5.8 Optimizing for Lowest Wakeup Latency.................................................................................................................. 153
2.5.9 Optimizing for Lowest Peak Current in RUN/SLEEP Mode.....................................................................................154
2.6 PMCU Registers............................................................................................................................................................ 154
2.6.1 SYSCTL Registers.................................................................................................................................................. 155
3 CPU...................................................................................................................................................................................... 213
3.1 Overview........................................................................................................................................................................ 214
3.2 Arm Cortex-M0+ CPU.................................................................................................................................................... 214
3.2.1 CPU Register File....................................................................................................................................................215
3.2.2 Stack Behavior........................................................................................................................................................ 217
3.2.3 Execution Modes and Privilege Levels....................................................................................................................217
3.2.4 Address Space and Supported Data Sizes............................................................................................................. 217
3.3 Interrupts and Exceptions.............................................................................................................................................. 218
3.3.1 Peripheral Interrupts (IRQs).................................................................................................................................... 219
3.3.2 Interrupt and Exception Table..................................................................................................................................223
3.3.3 Processor Lockup Scenario.....................................................................................................................................225
3.4 CPU Peripherals............................................................................................................................................................ 225
3.4.1 System Control Block (SCB)................................................................................................................................... 225
3.4.2 System Tick Timer (SysTick)................................................................................................................................... 226
3.4.3 Memory Protection Unit (MPU)................................................................................................................................226
3.5 Read-only Memory (ROM)............................................................................................................................................. 228
3.6 CPUSS Registers...........................................................................................................................................................229
3.7 WUC Registers...............................................................................................................................................................263
4 DMA......................................................................................................................................................................................265
4.1 DMA Overview............................................................................................................................................................... 266
4.2 DMA Operation.............................................................................................................................................................. 267
4.2.1 Addressing Modes...................................................................................................................................................267
4.2.2 Channel Types.........................................................................................................................................................269
4.2.3 Transfer Modes........................................................................................................................................................270
4.2.4 Extended Modes......................................................................................................................................................271
4.2.5 Initiating DMA Transfers.......................................................................................................................................... 273
4.2.6 Stopping DMA Transfers......................................................................................................................................... 273
4.2.7 Channel Priorities.................................................................................................................................................... 273
4.2.8 Burst Block Mode.................................................................................................................................................... 274
4.2.9 Using DMA with System Interrupts..........................................................................................................................274
4.2.10 DMA Controller Interrupts......................................................................................................................................274
4.2.11 DMA Trigger Event Status..................................................................................................................................... 274
4.2.12 DMA Operating Mode Support.............................................................................................................................. 275
4.2.13 DMA Address and Data Errors.............................................................................................................................. 275
4.2.14 Interrupt and Event Support.................................................................................................................................. 276
4.3 DMA Registers............................................................................................................................................................... 277
5 MATHACL............................................................................................................................................................................ 325
5.1 Overview........................................................................................................................................................................ 325
5.2 Data Format................................................................................................................................................................... 325
5.2.1 Unsigned 32-bit integers..........................................................................................................................................325
5.2.2 Signed 32-bit integers..............................................................................................................................................325
5.2.3 Unsigned 32-bit numbers........................................................................................................................................ 326
5.2.4 Signed 32-bit numbers............................................................................................................................................ 326
5.3 Basic Operation..............................................................................................................................................................326
5.4 Configuration Details with Examples..............................................................................................................................327
5.4.1 Sine and Cosine (SINCOS)..................................................................................................................................... 327
5.4.2 Arc Tangent (ATAN2)............................................................................................................................................... 328
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5.4.3 Square Root (SQRT)............................................................................................................................................... 330
5.4.4 Division (DIV)...........................................................................................................................................................331
5.4.5 Multiplication............................................................................................................................................................333
5.4.6 Multiply-Accumulate (MAC)..................................................................................................................................... 337
5.4.7 Square Accumulate (SAC)...................................................................................................................................... 339
5.5 MATHACL Registers...................................................................................................................................................... 341
6 NVM (Flash)......................................................................................................................................................................... 353
6.1 NVM Overview............................................................................................................................................................... 354
6.1.1 Key Features........................................................................................................................................................... 354
6.1.2 System Components............................................................................................................................................... 354
6.1.3 Terminology............................................................................................................................................................. 354
6.2 Flash Memory Bank Organization..................................................................................................................................355
6.2.1 Banks.......................................................................................................................................................................355
6.2.2 Flash Memory Regions............................................................................................................................................355
6.2.3 Addressing...............................................................................................................................................................355
6.2.4 Memory Organization Examples............................................................................................................................. 356
6.3 Flash Controller..............................................................................................................................................................357
6.3.1 Overview of Flash Controller Commands................................................................................................................358
6.3.2 NOOP Command.................................................................................................................................................... 358
6.3.3 PROGRAM Command............................................................................................................................................ 358
6.3.4 ERASE Command...................................................................................................................................................363
6.3.5 READVERIFY Command........................................................................................................................................ 363
6.3.6 BLANKVERIFY Command...................................................................................................................................... 364
6.3.7 Command Diagnostics............................................................................................................................................ 365
6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address.................................................... 365
6.3.9 FLASHCTL Events.................................................................................................................................................. 366
6.4 Write Protection..............................................................................................................................................................366
6.4.1 Write Protection Resolution..................................................................................................................................... 366
6.4.2 Static Write Protection............................................................................................................................................. 367
6.4.3 Dynamic Write Protection........................................................................................................................................ 367
6.5 Read Interface................................................................................................................................................................368
6.5.1 Bank Address Swapping......................................................................................................................................... 368
6.5.2 ECC Error Handling.................................................................................................................................................368
6.6 FLASHCTL Registers.....................................................................................................................................................369
7 Events.................................................................................................................................................................................. 435
7.1 Events Overview............................................................................................................................................................ 436
7.1.1 Event Publisher....................................................................................................................................................... 436
7.1.2 Event Subscriber..................................................................................................................................................... 436
7.1.3 Event Fabric Routing............................................................................................................................................... 436
7.1.4 Event Routing Map.................................................................................................................................................. 438
7.1.5 Event Propagation Latency..................................................................................................................................... 439
7.2 Events Operation........................................................................................................................................................... 440
7.2.1 CPU Interrupt...........................................................................................................................................................440
7.2.2 DMA Trigger............................................................................................................................................................ 440
7.2.3 Peripheral to Peripheral Event.................................................................................................................................441
7.2.4 Extended Module Description Register................................................................................................................... 442
7.2.5 Using Event Registers............................................................................................................................................. 442
8 IOMUX.................................................................................................................................................................................. 445
8.1 IOMUX Overview............................................................................................................................................................446
8.1.1 IO Types and Analog Sharing..................................................................................................................................446
8.2 IOMUX Operation...........................................................................................................................................................449
8.2.1 Peripheral Function (PF) Assignment......................................................................................................................449
8.2.2 Logic High to Hi-Z Conversion.................................................................................................................................449
8.2.3 Logic Inversion........................................................................................................................................................ 450
8.2.4 SHUTDOWN Mode Wakeup Logic..........................................................................................................................450
8.2.5 Pullup/Pulldown Resistors....................................................................................................................................... 451
8.2.6 Drive Strength Control............................................................................................................................................. 451
8.2.7 Hysteresis and Logic Level Control......................................................................................................................... 451
8.3 IOMUX (PINCMx) Register Format................................................................................................................................453
8.4 IOMUX Registers........................................................................................................................................................... 455
9 GPIO.....................................................................................................................................................................................459
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SLAU846 – JUNE 2023
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MSPM0 G-Series 80-MHz Microcontrollers 5
Copyright © 2023 Texas Instruments Incorporated
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