################################################################################
# Vivado (TM) v2017.4 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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基于FPGA的全相位傅里叶变化实现 (734个子文件)
xsim.ini.bak 19KB
elaborate.bat 1KB
compile.bat 968B
simulate.bat 845B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
apfft.bd 11KB
apfft.bxml 4KB
xsim_10.c 1.08MB
sin_60.coe 41KB
cos_20.coe 41KB
sin_60.coe 41KB
cos_20.coe 41KB
cos_20.coe 41KB
cos_45.coe 41KB
cos_45.coe 41KB
cos_45.coe 41KB
sin_60.coe 41KB
sin_60.coe 41KB
sin_60.coe 41KB
sin_60.coe 41KB
sin_60.coe 41KB
sin_60.coe 41KB
sin_60.coe 41KB
sin_60.coe 41KB
xsim.dbg 194KB
apfft_fourier_0_1.dcp 4.62MB
apfft_fourier_0_1.dcp 4.62MB
xfft_0.dcp 4.56MB
apfft_arctan_0_0.dcp 906KB
apfft_arctan_0_0.dcp 906KB
cordic_0.dcp 825KB
apfft_preprocess_0_0.dcp 148KB
apfft_preprocess_0_0.dcp 148KB
apfft_data_source_0_2.dcp 58KB
apfft_data_source_0_2.dcp 58KB
blk_mem_gen_1.dcp 52KB
blk_mem_gen_0.dcp 48KB
blk_mem_gen_1.dcp 39KB
apfft_wrapper.dcp 17KB
compile.do 4KB
compile.do 3KB
compile.do 3KB
compile.do 3KB
compile.do 3KB
compile.do 3KB
compile.do 2KB
compile.do 2KB
compile.do 806B
compile.do 782B
compile.do 774B
compile.do 774B
compile.do 741B
compile.do 740B
compile.do 740B
compile.do 731B
compile.do 690B
compile.do 690B
compile.do 676B
compile.do 676B
simulate.do 633B
simulate.do 625B
simulate.do 625B
simulate.do 552B
simulate.do 546B
simulate.do 546B
elaborate.do 505B
elaborate.do 424B
simulate.do 341B
simulate.do 341B
simulate.do 340B
simulate.do 340B
simulate.do 340B
simulate.do 340B
simulate.do 303B
simulate.do 294B
simulate.do 294B
elaborate.do 213B
elaborate.do 213B
simulate.do 203B
simulate.do 203B
simulate.do 193B
simulate.do 189B
simulate.do 187B
elaborate.do 175B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
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