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This document is applicable for S905X3 series SoCs, please contact your Amlogic sales representa tive for details. S905X3 is an advanced application processor designed for hybrid OTT/IP Set Top Box(STB) and high-end media box applications. It integrates a powerful CPU/GPU subsystem, a powerful NPU(Neu ral Network Processing Unit) Optional , a secured 8K video CODEC engine and a best-in-class HDR im age processing pipeline with all major peripherals to form the ultimate low power multimedia
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S905X3
Datasheet
Revision: 02
Release Date: 2020-03-31
Confidential for Hardkernel!
02 (2020-03-31)
Amlogic Proprietary and Confidential
Copyright © Amlogic. All rights reserved.
i
Copyright
©2020 Amlogic. All rights reserved. No part of this document may be reproduced, transmitted, tran-
scribed, or translated into any language in any form or by any means without the written permission of
Amlogic.
Trademarks
, and other Amlogic icons are trademarks of Amlogic companies. All other trademarks and
registered trademarks are property of their respective holders.
Disclaimer
Amlogic may make improvements and/or changes in this document or in the product described in this
document at any time.
This product is not intended for use in medical, life saving, or life sustaining applications.
Circuit diagrams and other information relating to products of Amlogic are included as a means of illus-
trating typical applications. Consequently, complete information sufficient for production design is not
necessarily given. Amlogic makes no representations or warranties with respect to the accuracy or
completeness of the contents presented in this document.
Contact Information
�� Website: www.amlogic.com
�� Pre-sales consultation: contact@amlogic.com
�� Technical support: support@amlogic.com
Confidential for Hardkernel!
02 (2020-03-31)
Amlogic Proprietary and Confidential
Copyright © Amlogic. All rights reserved.
ii
Revision History
Issue 02 (2020-03-31)
This is the 02 version. Compared to the previous version, the following topics are changed:
Section Change Description
10
Updated the figure of audio path.
7.2.2
7.4
Deleted L2 cache description.
7.9.3.7
ModifIed the description of PAD_DS_REG2B register.
2
3
Updated HDCP 2.2 to HDCP 2.2/2.3.
Issue 01 (2019-12-06)
This is the 01 version. Compared to the previous version, the descriptions in several topics are
optimized.
Issue 0.2 (2019-11-21)
This is the 0.2 version.
Compared to the previous version, the following topic is added:
�� 1
Compared to the previous version, the following topics are changed:
Section Change Description
3
Changed the specification of H.264 video encoding.
5.5.1
Changed the maximum specification of R
pd
.
5.5.2
Added a note explaining “OD 5V”.
5.11
Changed the maximum current specification of VDDCPU and VDDQ.
Issue 0.1 (2019-06-04)
This is the initial release.
S905X3 Datasheet Revision History
Confidential for Hardkernel!
S905X3 Datasheet Contents
02 (2020-03-31)
Amlogic Proprietary and Confidential
Copyright © Amlogic. All rights reserved.
iii
Contents
Revision History ................................................................................................................................. ii
1 About This Document....................................................................................................................1
2 General Description.......................................................................................................................2
3 Features Summary ........................................................................................................................3
4 Pinout Specification ......................................................................................................................8
4.1 Pin-Out Diagram (top view) ....................................................................................................8
4.2 Pin Order ...............................................................................................................................8
4.3 Pin Description ....................................................................................................................12
4.4 Pin Multiplexing Tables ........................................................................................................23
4.5 Signal Description................................................................................................................28
5 Operating Conditions ..................................................................................................................36
5.1 Absolute Maximum Ratings .................................................................................................36
5.2 Recommended Operating Conditions ..................................................................................36
5.3 Ripple Voltage Specifications ...............................................................................................37
5.4 Thermal Resistance.............................................................................................................37
5.5 DC Electrical Characteristics................................................................................................38
5.5.1 Normal GPIO Specifications (For DIO_xmA) ..............................................................38
5.5.2 Open Drain GPIO Specifications (For DIO_OD) .........................................................39
5.5.3 DDR3/DDR3L/DDR4/LPDDR3/LPDDR4 SDRAM Specifications ................................40
5.6 Recommended Oscillator Electrical Characteristics..............................................................41
5.7 Timing Information ...............................................................................................................42
5.7.1 I2C Timing Specification ............................................................................................42
5.7.2 EMMC/SD Timing Specification .................................................................................43
5.7.3 NAND Timing Specification ........................................................................................48
5.7.4 SPICC Timing Specification .......................................................................................50
5.7.5 SPIFC Timing Specification........................................................................................51
5.7.6 Ethernet Timing Specification.....................................................................................52
5.7.7 Audio Timing Specification .........................................................................................55
5.7.8 PDM Timing Specification ..........................................................................................58
5.7.9 UART Timing Specification ........................................................................................59
5.8 Power On Config .................................................................................................................59
5.9 Power On Reset ..................................................................................................................60
5.10 Recommended Power on Sequence ..................................................................................61
5.11 Power Consumption...........................................................................................................62
5.12 Storage and Baking Conditions ..........................................................................................63
6 Mechanical Dimensions ..............................................................................................................64
7 System .........................................................................................................................................65
Confidential for Hardkernel!
S905X3 Datasheet Contents
02 (2020-03-31)
Amlogic Proprietary and Confidential
Copyright © Amlogic. All rights reserved.
iv
7.1 Memory Map........................................................................................................................65
7.2 Power Domain .....................................................................................................................68
7.2.1 Top Level Power Domains..........................................................................................69
7.2.2 A55 Power Modes......................................................................................................70
7.2.3 EE Top Level Power Modes .......................................................................................71
7.2.4 Register Description...................................................................................................74
7.3 System Booting ...................................................................................................................79
7.3.1 Overview ...................................................................................................................79
7.3.2 Power-on Flow Chart .................................................................................................79
7.4 CPU ....................................................................................................................................80
7.5 GPU ....................................................................................................................................81
7.6 NPU ....................................................................................................................................81
7.6.1 Overview ...................................................................................................................81
7.6.2 Register Description...................................................................................................83
7.7 Clock ...................................................................................................................................88
7.7.1 Overview ...................................................................................................................88
7.7.2 Clock Trees ...............................................................................................................89
7.7.3 Frequency Calculation ...............................................................................................97
7.7.4 Clock Gating ............................................................................................................104
7.7.5 Clock Measure.........................................................................................................109
7.7.6 Register Description................................................................................................. 112
7.8 Reset.................................................................................................................................153
7.8.1 Overview .................................................................................................................153
7.8.2 Register Description.................................................................................................153
7.9 GPIO .................................................................................................................................161
7.9.1 Overview .................................................................................................................161
7.9.2 GPIO Multiplex Function ..........................................................................................163
7.9.3 Register Description.................................................................................................170
7.10 Interrupt Control...............................................................................................................193
7.10.1 Overview ...............................................................................................................193
7.10.2 Interrupt Source .....................................................................................................193
7.10.3 GPIO Interrupt .......................................................................................................199
7.10.4 Register Description...............................................................................................201
7.11 Timer ...............................................................................................................................204
7.11.1 Overview................................................................................................................204
7.11.2 General-Purpose Timer ..........................................................................................204
7.11.3 Watchdog Timer.....................................................................................................205
7.11.4 Register Description...............................................................................................206
7.12 Crypto..............................................................................................................................215
7.12.1 Overview ...............................................................................................................215
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