S905
Datasheet
Revision: 1.1.4
Release date: 6/6/2016
Amlogic, Inc.
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COPYRIGHT
© 2015 Amlogic, Inc.
All rights reserved. No part of this document may be reproduced. Transmitted, transcribed, or translated into any language in
any form or by any means with the written permission of Amlogic, Inc.
TRADEMARKS
AMLOGIC is a trademark of Amlogic, Inc. All other trademarks and registered trademarks are property of their respective
companies.
DISCLAIMER
Amlogic Inc. may make improvements and/or changes in this document or in the product described in this document at any
time.
This product is not intended for use in medical, life saving, or life sustaining applications.
Circuit diagrams and other information relating to products of Amlogic Inc. are included as a means or illustrating typical
applications. Consequently, complete information sufficient for production design is not necessarily given. Amlogic makes no
representations or warranties with respect to the accuracy or completeness of the contents presented in this document.
REVISION HISTORY
Revision
Number
Revision Date
Changes
0.5
2015/7/18
Initial version release
1.0
2016/3/11
Add Information about crypto, video path, audio path, mermory interface, DDR,
Nand, PLLs, JTAG, temperature sensor, Int 32K osc and PerfMon information
1.1.4
2016/6/1
Add SHA-2 hash functions (SHA-224/SHA-256) supported in 3.3
CONTACT INFORMATION
Amlogic, Inc.
2518 Mission College Blvd, Suite 120
Santa Clara, CA 95054
U.S.A.
www.amlogic.com
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Contents
Section I About This Documentation ........................................................................................................................ 8
1. Documentation Overview .................................................................................................................................. 8
2. Acronyms and Abbreviations ............................................................................................................................. 8
Section II General Information ............................................................................................................................. 10
3. Features ........................................................................................................................................................... 11
3.1 CPU Architecture ...................................................................................................................................... 11
3.2 GPU Architecture ...................................................................................................................................... 11
3.3 Crypto Engine ........................................................................................................................................... 11
3.4 Video Path ................................................................................................................................................ 11
3.5 Audio Path ................................................................................................................................................ 12
3.6 Memory .................................................................................................................................................... 12
3.7 I/O Interfaces ............................................................................................................................................ 12
3.8 System Interface ....................................................................................................................................... 12
3.9 Power Management ................................................................................................................................. 12
3.10 Security ................................................................................................................................................. 13
4. System Block Diagram ..................................................................................................................................... 13
5. Pin-Out Diagram (Top view) ......................................................................................................................... 14
6. Pin Description ................................................................................................................................................. 14
7. Pin Multiplexing ............................................................................................................................................... 28
8. Signal Description ............................................................................................................................................ 30
9. Absolute Maximum Ratings ............................................................................................................................. 36
10. Recommended Operating Conditions .......................................................................................................... 36
11. Ripple Voltage Specifications ....................................................................................................................... 36
12. Thermal Operating Specifications ................................................................................................................ 37
13. DC Electrical Characteristics ......................................................................................................................... 38
13.1 Normal GPIO Specifications (For DIO_xmA) ......................................................................................... 38
13.2 Open Drain GPIO Specifications (For DIO_OD) ..................................................................................... 38
13.3 DDR3/LPDDR2/LPDDR3 SDRAM Specifications .................................................................................... 38
13.4 Recommended Oscillator Electrical Characteristics ............................................................................. 40
14. Recommended Power on sequence ............................................................................................................ 40
15. Power Consumption ..................................................................................................................................... 41
16. Mechanical Dimension ................................................................................................................................. 41
Section III System ................................................................................................................................................... 44
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17. Memory Map ............................................................................................................................................... 44
18. Power Domain .............................................................................................................................................. 46
18.1 Top Level Power Domains..................................................................................................................... 47
18.2 A53 Power Modes ................................................................................................................................. 47
18.3 EE Top Level Power Modes ................................................................................................................... 48
18.4 Mali Power Modes ................................................................................................................................ 48
18.5 Power/Isolation/Memory Power Down Register Summary ................................................................. 49
19. System Booting ............................................................................................................................................ 51
19.1 Overview ............................................................................................................................................... 51
19.2 Power-on Flow Chart ............................................................................................................................ 51
20. CPU ............................................................................................................................................................... 52
20.1 Overview ............................................................................................................................................... 52
21. GPU .............................................................................................................................................................. 52
22. Clock and Reset ............................................................................................................................................ 53
22.1 Overview ............................................................................................................................................... 53
22.2 Clock Trees ............................................................................................................................................ 53
22.3 Clock Gating .......................................................................................................................................... 56
22.4 Register Description .............................................................................................................................. 60
23. GPIO ............................................................................................................................................................. 80
23.1 Overview ............................................................................................................................................... 80
23.2 GPIO Multiplex Function ....................................................................................................................... 80
23.3 GPIO Interrupt ...................................................................................................................................... 86
23.4 Register Description .............................................................................................................................. 87
24. Interrupt Control .......................................................................................................................................... 88
24.1 Overview ............................................................................................................................................... 88
24.2 Interrupt Source .................................................................................................................................... 88
24.3 Register Description .............................................................................................................................. 92
25. DIRECT MEMORY ACCESS CONTROLLER (DMAC) ........................................................................................ 93
25.1 Overview ............................................................................................................................................... 93
25.2 Descriptor Table .................................................................................................................................... 93
25.3 Register Description .............................................................................................................................. 94
26. TIMER ........................................................................................................................................................... 99
26.1 Overview ............................................................................................................................................... 99
26.2 General-Purpose Timer ......................................................................................................................... 99
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26.3 Watchdog Timer ................................................................................................................................... 99
26.4 Register Definitions ............................................................................................................................. 100
27. Crypto ......................................................................................................................................................... 104
27.1 Overview ............................................................................................................................................. 104
27.2 Key Ladder .......................................................................................................................................... 104
27.3 RNG ..................................................................................................................................................... 104
27.4 EFUSE .................................................................................................................................................. 104
Section IV Video Path ........................................................................................................................................... 106
28. Video Input ................................................................................................................................................. 106
28.1 Overview ............................................................................................................................................. 107
28.2 Demux ................................................................................................................................................. 107
28.3 DVP...................................................................................................................................................... 107
28.4 Register Definition .............................................................................................................................. 107
29. Video Output .............................................................................................................................................. 124
29.1 CVBS .................................................................................................................................................... 124
Section V Audio Path .......................................................................................................................................... 182
30. Audio_Input ............................................................................................................................................... 182
30.1 Overview ............................................................................................................................................. 182
30.2 SPIDF ................................................................................................................................................... 182
30.3 I2S(decode) ......................................................................................................................................... 183
30.4 PCM(decode) ...................................................................................................................................... 183
30.5 PDM .................................................................................................................................................... 183
30.6 To_ddr ................................................................................................................................................. 183
30.7 Register Description ............................................................................................................................ 185
31. Audio Output .............................................................................................................................................. 198
31.1 Overview ............................................................................................................................................. 198
31.2 SPDIF(encode) ..................................................................................................................................... 198
31.3 I2S(encode) ......................................................................................................................................... 199
31.4 Register Description ............................................................................................................................ 201
Section VI Memory INTERFACE ............................................................................................................................ 220
32. DDR ............................................................................................................................................................ 220
32.1 Overview ............................................................................................................................................. 220
32.2 Register Description ............................................................................................................................ 221
33. NAND .......................................................................................................................................................... 274
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