arm指令集pdf文件

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arm指令集
ARM Instruction Set 4.1.2 Instruction summary Mnemonic Instruction Action See section ADC Add with carry Rd: =Rn + Op2 Carry 4.5 ADD Rd: =Rn Op2 4.5 AND AND Rd: =Rn AND Op2 4.5 B Branch R15:= address 4.4 BIC Bit clear Rd: Rn AND NOT Op2 4.5 BL Branch with Link R14 =R15. R15 address 4.4 BX Branch and Exchange R15:=Rn, 4.3 T bit: =Rn[O] CDP Coprocesor Data Processing(Coprocessor-specific 4.14 CMN Compare Negative CPSR flags: =Rn Op2 CMP Compare CPSR flags = Rn-Op2 4.5 EOR Exclusive OR Rd: =(Rn AND NOT Op2 4.5 OR(op2 AND NOT Rn) LDC Load coprocessor from Coprocessor load 4.15 memory LDM Load multiple registers Stack manipulation(Pop) 4.11 LDR Load register from memory Rd: =(address) 4.9,4.10 MCR Move cPU register to cRn: = rRn <op>cRm 4.16 coprocessor register MLA Multiply Accumulate Rd:=(Rm“Rs)+Rn 4.7.4.8 MOV Move register or constant Rd: = Op2 4.5 MRC Move from coprocessor Rn: =cRn (<op>cRm) register to CPU register MRS Move PSR status/flags to Rn: =PSR 4.6 register MSR Move register to PSR PSR Rm 4.6 status/flags UL Multiply Rd = Rm * Rs 4.7,4.8 MVN Move negative register Rd: =OXFFFFFFFF EOR Op2 4.5 ORR OR Rd: =Rn OR Op2 4.5 RSB Reverse Subtract Rd: =Op2-Rn 4.5 RSC Reverse Subtract with Carry Rd: =Op2-Rn-1+Carry45 Table 4-1: The arM Instruction set a ARM7TDMI-S Data Sheet 4-3 ARM DDI 0084D ARM Final- Open Access ARM Instruction Set Mnemonic Instruction Action See Section: SBC Subtract with Carry Rd: =Rn-Op2 -1+ Carry 4.5 STC Store coprocessor register to address: = CRn 4.15 memory ST Store Multiple Stack manipulation(Push) 4.11 STR Store register to memory <address>' Rd 4.9.4.10 SUB Subtract Rd: =Rn-Op2 4.5 SWI Software Interrupt sca‖l 4.13 SWP Swap register with memory Rd: =[Rn] [Rn]: =Rm 4.12 TEQ Test bitwise equality y CPSR flags: =Rn EOR Op24.5 TST Test bits CPSR flags =Rn AND Op24.5 Table 4-1: The ARM Instruction set (Continued) 4-4 ARM7TDMI-S Data Sheet 3 ARM DDI 0084D ARI Final -Open Access ARM Instruction Set 4.2 The Condition field In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instructions condition field. This field(bits 31: 28) determines the circumstances under which an instruction is to be executed. If the state of the C, N, z and v flags fulfils the conditions encoded by the field the instruction is executed, otherwise it is ignored There are sixteen possible conditions, each represented by a two-character suffix that can be appended to the instructions mnemonic. For example, a Branch(B in assembly language)becomes BEQ for"Branch if Equal", which means the Branch will only be taken if the Z flag is set In practice, fifteen different conditions may be used: these are listed in Table 4-2 Condition code summary. The sixteenth(1111)is reserved, and must not be used In the abs of a suffix the condition field of most instructions is set to"always"(sufi AL). This means the instruction will always be executed regardless of the CPSR condition codes Code Suffix Flags Meaning EQ Z set equal 0001 NE Z cleal lot equal 0010 C set unsigned higher or same 0011 CC C clear unsigned lower 0100 N set negative 0101 n clea sitive 0110 overflow 0111 VC Clear no overflow 1000 C set and z clear unsigned higher 1001 C clear or Z set unsigned lower or same 1010 N equals∨ greater or e 1011 LT N not equal to v less than 1100 GT Z clear AND(N equals v) greater than 1101 E Z set OR(n not equal to less than or equal 1110 (ignored) always Table 4-2: Condition code summary a ARM7TDMI-S Data Sheet ARM DDI 0084D ARM Final- Open Access ARM Instruction set 4.3 Branch and Exchange(BX) This instruction is only executed if the condition is true. the various conditions are defined in Table 4-2: Condition code summary on page 4-5 This instruction performs a branch by copying the contents of a general register, Rn into the program counter, PC. The branch causes a pipeline flush and refill from the address specified by Rn This instruction also permits the instruction set to be exchanged. When the instruction is executed, the value of rn[o determines whether the instruction stream will be decoded as arm or thumb instructions 2423 1615 1211 cond|000100101111111111110001Rn Operand register If bit o ot rn=0 subsequent instructions decoded as arm instruction Condition field Figure 4-2: Branch and Exchange instructions 4.3.1 Instruction cycle times The BX instruction takes 2S+ 1N cycles to execute, where S and n are as defined in 6.2 Cycle Types on page 6-3 4.3.2 Assembler syntax BX-branch and exchange BX(cond) Rn icond Two character condition mnemonic. See Table 4-2: Condition code summary on page 4-5 Rn is an expression evaluating to a valid register number 4.3.3 Using R15 as an operand If R15 is used as an operand the behaviour is undefined 4-6 ARM7TDMI-S Data Sheet 3 ARM DDI 0084D ARM: Final- Open Access ARM Instruction Set 4.3.4 Examples ADR RO, Into ThUMB +l; Generate branch target address i and set bit o high -hen i arrive in THUMB state CODE6 Assemble subsequent code as Intc THUMB i THUMB instructions ADR R5, Back to ARM: Generate branch target to word address -hence bit 0 ;is low and so change back t ARM BX R5 Branch and change back tc ARM ALIGN CODE3 Assemble subsequent code as ArM Back to ARM instruction a ARM7TDMI-S Data Sheet 4-7 ARM DDI 0084D ARM Final- Open Access ARM Instruction set 4. 4 Branch and Branch with Link(B, BL) The instruction is only executed if the condition is true. the various conditions are defined Table 4-2: Condition code summary on page 4-5. The instruction encoding is shown in Figure 4-3: Branch instructions, below 2827 52423 0 Cond 101 offset Link bit Condition field Figure 4-3: Branch instructions Branch instructions contain a signed 2's complement 24 bit offset. This is shifted left two bits, sign extended to 32 bits, and added to the pc. The instruction can therefore specify a branch of +/-32Mbytes The branch offset must take account of the prefetch operation, which causes the PC to be 2 words(8 bytes ) ahead of the current instruction Branches beyond +/-32Mbytes must use an offset or absolute destination which has been previously loaded into a register. In this case the PC should be manually saved in R14 if a branch with Link type operation is required 4. 4.1 The link bit Branch with Link (BL)writes the old Pc into the link register(R14 )of the current bank The Pc value written into R14 is adjusted to allow for the prefetch, and contains the address of the instruction following the branch and link instruction. Note that the CPSR is not saved with the Pc and r14[1: 0] are always cleared To return from a routine called by Branch with Link use MoV PC, R14 if the link register is still valid or LDM Rn! .PC) if the link register has been saved onto a stack pointed to by r 4.4.2 Instruction cycle times Branch and Branch with Link instructions take 2S 1N incremental cycles, where S and n are as define 6.2 Cycle Types on page 6-3 4-8 ARMZTDMI-S Data sheet ARM DDI 0084D ARI Final -Open Access ARM Instruction Set 4.4.3 Assembler syntax Items in t are optional Items in < must be present BILJicond <expression> L is used to request the branch with Link form of the instruction If absent, R14 will not be affected by the instruction Con is a two-character mnemonic as shown in Table 4-2 Condition code summary on page 4-5. If absent then AL ALways)will be used ≤ express|on> is the destination the assembler calculates the offset 4.4.4 Examples here BAL here i assembles to cxEAfffFfe (note effect of PC offset) dition used as CMD R1,#C i Compare Rl with zero and branch to fred if Rl was zero, otherwise continue BEQ fred continue to next instruction sutro Call subroutine at computed address ADDS R1,#1 Add 1 to register 1r setting CPsr flags on the result then call subroutine if BLCC sub ;the C flag is Clear, which will be the case unless R1 held CxFFFFEFFF a ARM7TDMI-S Data Sheet 4-9 ARM DDI 0084D ARM Final- Open Access ARM Instruction set 4.5 Data Processing The data processing instruction is only executed if the condition is true. The conditions are defined in Table 4-2: Condition code summary on page 4-5 The instruction encoding is shown in Figure 4-4: Data processing instructions below 2827262524 212019 l615 Cond 001 OpCode S Rd Operand 2 Destination register 1st operand register Set condition codes 1= set condition codes Operation Code 0010= SUB-Ro: =Op1-O 0011= RSB-Rc: Cp2-Op1 0101= ADC.Rd: Op1 Op2 t C 0110=sEc·Rc;=0p10p2+c·1 1001=TEQ-set conditian codes cn Op1 EOR Op2 1010=CMP-sct condition codcs on Op1-Or 1011=CMN-set conditon codes on Op1+op2 1100= ORR-Rd: =Op1 OR Op2 1111=MVN-Rd: NOT Op2 Immediate operand Shift Rm 2nd shift applied to Rm 1=operand 2 is an immediate value Rotate Imm Unsigned 8 bit immediate value Condition field Figure 4-4: Data processing instructions The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. The first operand is always a register(Rn) 4-10 ARM7TDMI-S Data Sheet 3 ARM DDI 0084D ARM: Final- Open Access

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