ARMv8 arm64 指令集速览表(打印版)

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ARMv8 arm64 指令集速览表(打印版)。包含了全部汇编指令,两页pdf,适合速查,可以打印在A4纸上方便编程。
ARMv8-A System ID Registers Generic timer registers MIDR.ELl Main id ROL JCNTFRQELO 〔 t Frequency (in hz Contral and Translation registers MPIDR ELI processor Affinity RO d NT VCT ELD C(Physicl itay Count R64 SCTLREL 13 System Control REVIDR.ELI Revision d ROL CNTVOFF_ EL2 Ct virtual offset ACTLR EL 1.3) Auxiliary Control CCSIDR EL Current cache size iD ROL CNTHCTLELL Ct hypervisor Control CPACREL1 Architectural Feature Access Control CLIDREL1 〔 ache level d RO CNTKCTLELI Ct Kernel contral HCREL2 64AE1 Auxiliary ID RO CNT(P, V)(TVAL, CT L, CVAL] ELO Ct(Physical, itua) Timer 〔PTRE23 Architectural Feature Trap CSSELR EL1 Cache size selection CNTHP. (TVAL CTL CVAL). EL2 Ct Hypervisor Physical Timer HSTR EL2 visor System Irap CTRELO Cache type RO CNTPS-TVAL TL, CVAL _ELI Ct Physical Secure Timer HACR EL2 Hyp pervsor Auxiliary Contral DCZID.ELO Data cache zero d RO CNTHV- TVAL, CTL CVAL ). EL2 Ct Virtual Timer SCREL3 Secure configuration VPIDREL2 Virtua ization Processor D TBB379小9 MMPIDR EL2 Virtualization Multiprocessor ID TBE7小m6ens0(地n TCR.EL 1.3 Translation Control 8160(60ME-订如 VtCREL2 Virt Translation Control (AJMAIR EL( 13) Auxiliary) Memory Atribute Indirection 64 LOR (SE AELI LORegion ( Start, End Address 64,1 ICONTEXTIDR ELI Context iD LOR(C,N, D ELI LORegion Cantrol, Number,ID K 641TPIDR EL(0-3 Software Thread D TPIDRRO ELO ELO Re2d-nl Sofware Thread Id 64 oa1, 0 1 SM intruction exection in Arch( 32.64 state Exception Registers Exception Vectors ESREL 1.3 Exception Syndrome FAR EL 1.3 Fault Address HPFAR-EL2 Hypervisor IPA Fault Adress PAR ELI Phvsical addre VBAR.EL[ 1.3 Vector Base Address(%kb aligned) RVBAR EL 1.3 Reset Vector Base Address RMR EL 1.3 Reset Management M Cx 0000001 MMU enab SREL1 Interrupt status c 0x00000004 Data and unified caches enabled Performance monitors registers PMCR ELO PM Control SAO (x000010 Enable Sp align ment check for ELO E1 Secure Configuration Register(SCR) PMCNTEN SET, CLR) ELO PM Count Enable (Set, Clear UMA Ox0C000200 Trap ELO access of DAlf to ELl Cx0001 System state is non-secure unless in EL3 PMOVSCLR ELO PM Overflow Flag Status Clear Cx 00001000 Instruction cache enabled IRQ 0X0002 RQs taken to EL3 PMSWINC ELO PM Sotware increment WO E1 FIQ ON004 FIQs taken to EL3 PMSELRELO PM Event Counter Selection O x000B External aborts and SError taken to EL3 PMCEID(O,_EL0 PM Common Event ID 0,19 E1 SMD (x0080 Secure monitor call disable PMCCNTR ELO PM Cycle Count Register nTWE OX0C040000 Trap ELO WFE instruction to ELl E1 HCE Cx0100 Hyp Call enable PMXEVTYPER ELO PM Selected Event Type WXN Ox00080000 Write permission implies XN SIF ( 0200 Secure instruction fetch pmxevcntrelo PM Selected event count E11(040ce64 PMUSERENR_ELo PM User Enable El IST Cx080 Trap secure ELl to CNTPS registers to EL3 PMOVSSETEL PM Overflow Flag Status set EE Cx0Z00000 Data at ELl is big-endian PMINTENSET, CLR EL1 PM Interrupt Enable Set, Clear) UCI Ox04000 Trap ELO cache instructions to EL1 El TWE CX2000 Trap EL( 0. 2] WFE instruction to EL3 PMEVCNTR0. 30 -ELO PM Event Count 0.301 PMEVTYPER(0.30_ELO PM Event Type(0. 30) PMCCFILTRELo PM Cycle Count Filter vers.on 2 page

试读 3P ARMv8 arm64 指令集速览表(打印版)
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