GC9503V-DSIC规格书_mipi屏初始化参数资源-CSDN文库

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GC9503V

a-Si TFT LCD Single-Chip Driver 480(RGB)x864

Resolution, 16.7M-color Without internal GRAM

Specification

Version 1.00

2017.03.30

GalaxyCore Incorporation

GalaxyCore Inc. reserves the right to change the contents in this document without prior notice.

GC9503V

List of Content

List of Content ................................................................................................................................................. 2

1 DESCRIPTION............................................................................................................................................. 5

2 FEATURES .................................................................................................................................................. 6

3 BLOCK DIAGRAM .................................................................................................................................... 8

4 PIN DESCRIPTION ................................................................................................................................... 11

4.1 PIN DESCRIPTION ........................................................................................................................ 11

4.2 Output Bump Dimension ................................................................................................................. 15

4.3 Input Bump Dimension .................................................................................................................... 16

4.4 Alignment Mark Dimension ............................................................................................................ 17

4.5 Chip Information .............................................................................................................................. 17

4.6 Pad Coordination ............................................................................................................................. 18

5 System Interface .......................................................................................................................................... 27

5.1 Interface Type Selection .................................................................................................................. 27

5.2 SPI Interface ..................................................................................................................................... 28

5.2.1 SPI-8BIT/9BIT Write Cycle Sequence ................................................................................. 28

5.2.2 SPI-8BIT/9BIT Read Cycle Sequence.................................................................................. 30

5.2.3 Data Transfer Break and Recovery ....................................................................................... 31

5.3 DPI (RGB) Interface ........................................................................................................................ 33

5.3.1DPI Interface Selection .......................................................................................................... 33

5.3.2 DPI Interface Timing............................................................................................................. 35

5.4 DSI system interface ........................................................................................................................ 36

5.4.1 General Description .............................................................................................................. 36

5.4.2 Interface Level Communication ............................................................................................ 37

5.4.3 DSI-CLK Lanes .................................................................................................................... 38

5.4.4 Low Power Mode (LPM) ...................................................................................................... 39

5.4.5 Ultra Low Power Mode (ULPM) .......................................................................................... 41

5.4.5 High-Speed Clock Mode (HSCM) ........................................................................................ 42

5.4.6 DSI-D1 and DSI-D0 Data Lanes ........................................................................................... 44

5.4.7 Escape Modes ....................................................................................................................... 45

5.4.8 Low-Power Data Transmission (LPDT) ............................................................................... 47

5.4.9 Ultra-Low Power State (ULPS) ............................................................................................ 48

5.4.10 Remote Application Reset (RAR) ...................................................................................... 49

5.4.11 Acknowledge (ACK) .......................................................................................................... 50

5.4.12 Entering High-Speed Data Transmission (TSOT of HSDT) .............................................. 51

5.4.13 Leaving High-Speed Data Transmission (TEOT of HSDT) ............................................... 52

5.4.14 Burst of the High-Speed Data Transmission (HSDT) ......................................................... 53

5.4.15 Bus Turnaround (BTA) ....................................................................................................... 57

5.4.16 Packet Level Communication ............................................................................................. 58

5.4.17 Short Packet (SPa) and Long Packet (LPa) Structures ....................................................... 58

5.4.18 Bit Order of the Byte on Packets ........................................................................................ 59

5.4.19 Byte Order of the Multiple Byte Information on Packets ................................................... 59

5.4.20 Packet Header (PH)............................................................................................................. 60

5.4.21 Data Identification (DI)....................................................................................................... 61

5.4.22 Virtual Channel (VC) .......................................................................................................... 62

5.4.23 Data Type (DT) ................................................................................................................... 63

GC9503V

5.4.24 Packet Data (PD) on the Short Packet (SPa) ....................................................................... 65

5.4.25 Word Count (WC) on the Long Packet (LPa) .................................................................... 66

5.4.26 Error Correction Code (ECC) ............................................................................................. 67

5.4.27 Packet Data (PD) on the Long Packet (LPa) ....................................................................... 72

5.4.28 Packet Footer (PF) on the Long Packet (LPa) ..................................................................... 72

5.4.29 Packet Transmissions .......................................................................................................... 74

5.4.30 Packet from the MPU to the Display Module ..................................................................... 74

5.4.31 Display Command Set (DCS) ............................................................................................. 74

5.4.32 Display Command Set (DCS) Write, No Parameter (DCSWN-S) ..................................... 75

5.4.33 Display Command Set (DCS) Write, 1 Parameter (DCSW1-S) ......................................... 76

5.4.34 Display Command Set (DCS) Write Long (DCSW-L) ....................................................... 77

5.4.35 Display Command Set (DCS) Read, No Parameter (DCSRN-S) ....................................... 81

5.4.36 Null Packet, No Data (NP-L) .............................................................................................. 84

5.4.37 Packet from the Display Module to the MPU ..................................................................... 88

5.4.38 Used Packet types ............................................................................................................... 88

5.4.39 Acknowledge with Error Report (AwER) ........................................................................... 90

5.4.40 DCS Read Long Response (DCSRR-L) .............................................................................. 94

5.4.41 DCS Read Short Response, 1 Byte Returned (DCSRR1-S) ................................................ 96

5.4.42 DCS Read Short Response, 2 Bytes Returned (DCSRR2-S) .............................................. 97

5.4.43 Communication Sequences ................................................................................................. 98

5.4.44 Sequences ............................................................................................................................ 99

5.4.45 DCS Write, 1 Parameter Sequence ..................................................................................... 99

5.4.46 DCS Write, No Parameter Sequence ................................................................................ 100

5.4.47 DCS Write Long Sequence ............................................................................................... 101

5.4.48 DCS Read, No Parameter Sequence ................................................................................. 102

5.4.49 Null Packet, No Data Sequence ........................................................................................ 103

5.4.50 End of Transmission Packet .............................................................................................. 103

5.5 Display Data Format ...................................................................................................................... 104

5.5.1 DPI (RGB) Interface ........................................................................................................... 104

5.5.2 16-bit / pixel 65K colors order on the DPI Interface ........................................................... 104

5.5.3 18-bit / pixel 262K colors order on the DPI Interface ......................................................... 105

5.5.4 24-bit / pixel 16.7M colors order on the DPI Interface ....................................................... 106

5.5.5 DSI transmission data format .............................................................................................. 107

5.5.6 16-bit per Pixel, Long packet, Data Type 00 1110 (0Eh) ................................................... 107

5.5.7 18-bit per Pixel, Long packet, Data Type = 01 1110 (1Eh) ................................................ 108

5.5.8 24-bit per Pixel, Long packet, Data Type = 11 1110 (3Eh) ................................................ 110

6. Command ................................................................................................................................................. 111

6.1 User Command Set ........................................................................................................................ 111

Read Display ID (04h) ................................................................................................................. 113

Read DSI ERROR (05h) .............................................................................................................. 114

Read Display Power Mode (0Ah) ................................................................................................ 115

Read Display MADCTL (0Bh) .................................................................................................... 116

Read Display Pixel Format (0Ch) ................................................................................................ 117

Read Display Image Mode (0Dh) ................................................................................................ 118

Sleep In (10h) ............................................................................................................................... 119

Sleep Out (11h) ............................................................................................................................ 120

Partial Mode On (12h) ................................................................................................................. 121

Normal Display Mode On (13h) .................................................................................................. 122

All Pixel Off (22h) ....................................................................................................................... 123

All Pixel On (23h) ........................................................................................................................ 124

Display Off (28h) ......................................................................................................................... 125

GC9503V

Display ON (29h) ......................................................................................................................... 126

Partial Area (30h) ......................................................................................................................... 127

Idle Mode Off (38h) ..................................................................................................................... 128

Idle Mode On (39h) ..................................................................................................................... 129

Interface Pixel Format (3Ah) ....................................................................................................... 130

Write Display Brightness Value (51h) ......................................................................................... 131

RGB Interface Signals Control(B0h) ........................................................................................... 132

DISPLAY_CTL (B1h) ................................................................................................................. 133

Read ID1 (DAh) ........................................................................................................................... 134

Read ID2 (DBh) ........................................................................................................................... 135

Read ID3 (DCh) ........................................................................................................................... 136

EXTC Command Set enable register (F0h) .................................................................................. 137

OTP_CTL (F6h) ........................................................................................................................... 138

6.2 Page 0 Command Set ..................................................................................................................... 139

VREG_CTL0 (80h) ..................................................................................................................... 140

VREG_CTL1 (82h) ..................................................................................................................... 141

CHP_CTL1 (86h)......................................................................................................................... 142

CHP_CTL2(89h).......................................................................................................................... 143

CHP_CTL3 (90h)......................................................................................................................... 144

CHP_CTL4 (91h)......................................................................................................................... 145

VREG_CTL2 (98h) ..................................................................................................................... 146

VREG_CTL3 (99h) ..................................................................................................................... 147

VREG_CTL4 (9Ah)..................................................................................................................... 148

VREG_CTL5 (9Bh) ..................................................................................................................... 149

CHP_CTL5(A0h) ......................................................................................................................... 150

7. Power ON/OFF Sequence ........................................................................................................................ 151

7.1. Case 1 –RESX line is held High or Unstable by Host at Power ON ............................................. 152

7.2. Case 2 – RESX line is held Low by Host at Power ON ................................................................ 153

7.3. Abnormal Power Off ..................................................................................................................... 154

8. Power Level Definition ........................................................................................................................... 155

8.1. LCM Voltage Generation ............................................................................................................. 155

9. Electrical Characteristics ......................................................................................................................... 156

9.1. Absolute Maximum Ratings ...................................................................................................... 156

9.2. DC Characteristics for Panel Driving ...................................................................................... 157

9.3. DSI DC Characteristics ............................................................................................................. 158

9.4 DC characteristics for Power Lines .......................................................................................... 158

9.5. DC characteristics for DSI LP mode ....................................................................................... 159

9.6. Spike / Glitch Rejection ............................................................................................................. 159

9.7. DC Characteristics for DSI HS mode ...................................................................................... 160

9.8. AC Characteristics ..................................................................................................................... 163

9.8.1. Display Serial Interface Timing Characteristics (3-line SPI system) .............................. 163

9.8.2. Parallel 24/18/16-bit RGB Interface Timing Characteristics........................................... 164

9.8.3. DSI Timing Characteristics.............................................................................................. 165

9.8.4. High Speed Mode – Clock Channel Timing .................................................................... 165

9.8.5. High Speed Mode – Data Clock Channel Timing ........................................................... 165

9.8.6 High Speed Mode – Rise and Fall Timings ..................................................................... 166

9.8.7. Low Speed Mode – Bus Turn Around ............................................................................. 167

9.8.8. Data Lanes from Low Power Mode to High Speed Mode............................................... 168

9.8.9. Data Lanes from High Speed Mode to Low Power Mode............................................... 169

9.8.10. DSI Clock Burst – High Speed Mode to/from Low Power Mode .................................. 170

10. Revision History .................................................................................................................................... 171