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Table of Contents
1.
Introduction ........................................................................................................................... 1
1.1. Goals and Objectives ........................................................................................................ 1
1.2. References ........................................................................................................................ 1
1.3. Definitions, abbreviations, and conventions...................................................................... 1
1.3.1. Definitions and Abbreviations .................................................................................... 1
1.3.2. Conventions ............................................................................................................... 3
2. Physical Interface ................................................................................................................. 6
2.1. TSOP-48 and WSOP-48 Pin Assignments ....................................................................... 6
2.2. LGA-52 Pad Assignments................................................................................................. 7
2.3. BGA-63 Ball Assignments................................................................................................. 8
2.4. Signal Descriptions ......................................................................................................... 11
2.5. CE# Signal Requirements............................................................................................... 14
2.6. Absolute Maximum Ratings ............................................................................................ 14
2.7. Recommended Operating Conditions............................................................................. 15
2.7.1. Provisions for I/O power (Vccq) and I/O ground (Vssq) .......................................... 15
2.8. DC and Operating Characteristics .................................................................................. 15
2.9. Calculating Pin Capacitance ........................................................................................... 17
2.10. Staggered Power-up.................................................................................................... 17
2.11. Independent Data Buses ............................................................................................. 18
2.12. Bus Width Requirements............................................................................................. 19
2.13. Ready/Busy (R/B#) Requirements .............................................................................. 19
2.13.1. Power-On Requirements...................................................................................... 19
2.13.2. R/B# and SR[6] relationship ................................................................................. 19
2.14. Write Protect................................................................................................................ 19
3. Memory Organization ......................................................................................................... 20
3.1. Addressing ...................................................................................................................... 21
3.1.1. Interleaved Addressing ............................................................................................ 21
3.1.2. Logical Unit Selection .............................................................................................. 22
3.1.3. Multiple LUN operation restrictions.......................................................................... 22
3.2. Factory Defect Mapping .................................................................................................. 23
3.2.1. Device Requirements............................................................................................... 23
3.2.2. Host Requirements .................................................................................................. 23
3.3. Discovery and Initialization.............................................................................................. 24
3.3.1. CE# Discovery ......................................................................................................... 24
3.3.2. Target Initialization................................................................................................... 25
3.4. Partial Page Programming.............................................................................................. 26
3.4.1. Requirements........................................................................................................... 26
3.4.2. Host Discovery......................................................................................................... 26
4. Timing Diagrams................................................................................................................. 27
4.1. Command Latch Timings ................................................................................................ 32
4.2. Address Latch Timings.................................................................................................... 33
4.3. Data Input Cycle Timings ................................................................................................ 34
4.4. Data Output Cycle Timings ............................................................................................. 35
4.5. Data Output Cycle Timings (EDO).................................................................................. 36
4.6. Read Status Timings....................................................................................................... 37
4.7. Read Status Enhanced Timings ..................................................................................... 38
5. Command Definition ........................................................................................................... 39
5.1. Command Set ................................................................................................................. 39
5.2. Reset Definition............................................................................................................... 40
5.3. Read ID Definition ........................................................................................................... 40
5.4. Read Parameter Page Definition .................................................................................... 41
5.4.1. Parameter Page Data Structure Definition .............................................................. 42
5.5. Read Unique ID Definition............................................................................................... 52
5.6. Block Erase Definition ..................................................................................................... 53
