################################################################################
# Vivado (TM) v2018.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA Xilinx 7系列高速收发器GTX通信工程代码
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FPGA Xilinx 7系列高速收发器GTX通信工程代码 (803个子文件)
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runme.bat 229B
runme.bat 229B
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runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
gtwizard_0_exdes.bit 16.61MB
top.bit 12.7MB
gt_rom_init_tx.dat 11KB
gt_rom_init_rx.dat 11KB
gt_rom_init_tx.dat 11KB
gt_rom_init_rx.dat 11KB
gt_rom_init_rx.dat 11KB
gt_rom_init_rx.dat 11KB
top_routed.dcp 2.41MB
gtwizard_0_exdes_routed.dcp 2.22MB
top_placed.dcp 2.15MB
gtwizard_0_exdes_placed.dcp 1.98MB
top_opt.dcp 1.49MB
gtwizard_0_exdes_opt.dcp 1.41MB
ila_0.dcp 594KB
ila_0.dcp 594KB
ila_0.dcp 593KB
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dbg_hub.dcp 357KB
dbg_hub.dcp 357KB
gtx_tx.dcp 131KB
gtx_tx.dcp 131KB
gtx_tx.dcp 130KB
gtx_tx.dcp 130KB
gtx_tx.dcp 130KB
top.dcp 104KB
gtwizard_0.dcp 92KB
gtwizard_0.dcp 92KB
gtwizard_0.dcp 92KB
gtwizard_0.dcp 91KB
gtwizard_0_exdes.dcp 51KB
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