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SLVS-EC
Specification
Version 1.2 xx July 2013
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USE RESTRICTION NOTICE
This USE RESTRICTION NOTICE (“Notice”) is for customers who are considering or currently
using the CMOS image sensor products or the DSP products (“Products”) integrated with SLVS-EC
interface set forth in this specification. Sony Corporation (“Sony”) may, at any time, modify this
Notice which will be available to you in the latest specification for SLVS-EC. You should abide by
the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice
on the Products, such a use restriction notice will additionally apply between you and the subsidiary
or distributor. You should consult a sales representative of the subsidiary or distributor of Sony
(“Sales Representative”) on such a use restriction notice when you consider using the Products with
SLVS-EC interface.
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without the permission of Sony.
Disclaimer
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information shown in this specification or for any infringement of third-party rights due to the same.
It is therefore your sole legal and financial responsibility to resolve any such problems and
infringement. THIS SPECIFICATION DOCUMENT IS PROVIDED "AS IS" AND WITHOUT
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TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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TECHNICAL INFORMATION SHOWN IN THIS SPECIFICATION WILL MEET YOUR
REQUIREMENTS. FURTHERMORE, SONY DOES NOT WARRANT OR MAKE ANY
REPRESENTATIONS REGARDING THE USE OR THE RESULTS OF THE USE OF THE
TECHNICAL INFORMATION SHOWN IN THIS SPECIFICATION IN TERMS OF ITS
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OR WRITTEN INFORMATION OR ADVICE GIVEN BY SONY OR A SONY AUTHORIZED
REPRESENTATIVE OR SALES REPRESENTATIVE SHALL CREATE A WARRANTY OR IN
ANY WAY INCREASE THE SCOPE OF THIS WARRANTY.
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The technical information shown in this specification is for your reference purposes only. The
availability of this specification shall not be construed as giving any indication that Sony and its
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Governing Law
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Other Applicable Terms and Conditions
The terms and conditions set forth in the Sony specifications, which will be made available to you
when you order the Products, shall apply to your use of the Products instead of this specification.
You should review those terms and conditions when you consider purchasing and/or using the
Products.
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Copyrights
The entire contents of this document are copyrighted by Sony.
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CONTENTS
1. Overview ...................................................................................................................................... 8
1.1. Scope ..................................................................................................................................... 8
1.2. Purpose .................................................................................................................................. 8
2. Reference Documents ................................................................................................................. 9
3. Definitions, acronyms, and abbreviations ................................................................................. 9
3.1. Definitions ............................................................................................................................ 9
3.2. Acronyms and abbreviations ................................................................................................. 9
4. Architecture ............................................................................................................................... 10
4.1. System Topology ................................................................................................................. 10
4.1.1. Basic Topology ........................................................................................................... 10
4.1.2. Multiple I/F Topology ................................................................................................. 11
4.1.3. Multiple CIS Topology ............................................................................................... 12
4.2. Frame Synchronization Scheme .......................................................................................... 13
4.2.1. DSP Master with shared clock .................................................................................... 13
4.2.2. DSP Master without shared clock ............................................................................... 13
4.2.3. CIS Master with shared clock ..................................................................................... 14
4.2.4. CIS Master without shared clock ................................................................................ 15
4.3. Hierarchical Structure ......................................................................................................... 16
4.3.1. Application Layer ....................................................................................................... 17
4.3.2. LINK Layer ................................................................................................................. 17
4.3.3. PHY Layer .................................................................................................................. 17
5. Application Layer Protocol Interface ...................................................................................... 18
5.1. RAW Pixel Data Format ..................................................................................................... 18
5.2. Embedded Data Transfer ..................................................................................................... 18
5.3. Frame Format ...................................................................................................................... 19
5.3.1. Single Stream Frame Format ...................................................................................... 19
5.3.2. Initialization ................................................................................................................ 20
5.3.3. Standby ....................................................................................................................... 21
5.3.4. Mode Change .............................................................................................................. 22
5.3.5. Mode Change with Standby ........................................................................................ 25
5.3.6. Interrupt....................................................................................................................... 26
5.4. Attribute and Configuration Register .................................................................................. 27
5.5. Multiple Stream Transfer .................................................................................................... 28
5.5.1. Frame Format of Multiple Stream Transfer ................................................................ 29
6. LINK Layer Specification ........................................................................................................ 30
6.1. Pixel to Byte Format Converter .......................................................................................... 30
6.1.1. Payload Data Format ................................................................................................... 34
6.2. Payload Data Error Correction ............................................................................................ 36
6.2.1. Payload Data Format with ECC .................................................................................. 37
6.3. Packetize ............................................................................................................................. 38
6.3.1. Packet Format ............................................................................................................. 38
6.3.2. Format and Protocol Error Handling ........................................................................... 40
6.4. Lane Management ............................................................................................................... 41
6.4.1. Lane Distribution ........................................................................................................ 42
6.4.2. Lane Distribution with Payload ECC .......................................................................... 43
6.5. LINK Protocol Management ............................................................................................... 44
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6.5.1. Packet Header Generation ........................................................................................... 44
6.5.2. Packet Footer Generation ............................................................................................ 46
6.5.3. Protocol Management FSM ........................................................................................ 48
7. PHY Layer Specification .......................................................................................................... 51
7.1. PHY Protocol Management ................................................................................................ 51
7.1.1. Protocol Management FSM ........................................................................................ 51
7.1.2. Training Sequence ....................................................................................................... 52
7.1.3. Packet Data Transfer Sequence ................................................................................... 53
7.1.4. Standby Sequence ....................................................................................................... 53
7.1.5. PHY Control Code ...................................................................................................... 54
7.2. Bandwidth Control .............................................................................................................. 54
7.3. Lane Skew Control ............................................................................................................. 56
7.4. Symbol Encoding ................................................................................................................ 57
7.5. Bit Ordering in Symbol Data .............................................................................................. 59
7.6. Symbol Alignment .............................................................................................................. 60
7.7. Baud Rate Scheme .............................................................................................................. 60
8. Electrical Characteristics ......................................................................................................... 61
8.1. TX Characteristics .............................................................................................................. 61
8.2. RX Characteristics .............................................................................................................. 62
8.3. Common Characteristics ..................................................................................................... 63
8.4. Interconnect Characteristics ................................................................................................ 64
Annex A. RX Analog Functional Specification ............................................................................... 65
Annex B. Implementation of Multiple Stream Transfer (Informative) ........................................ 70
Annex C. Frame format depending on CIS implementation ........................................................ 72
Annex D. RX Protocol Management FSM (Informative) .............................................................. 73
FIGURES
Figure 1 Basic Topology .................................................................................................................. 10
Figure 2 Multiple I/F Topology ....................................................................................................... 11
Figure 3 Multiple CIS Topology ...................................................................................................... 12
Figure 4 DSP Master with shared clock ........................................................................................... 13
Figure 5 DSP Master without shared clock ...................................................................................... 14
Figure 6 CIS Master with shared clock ............................................................................................ 15
Figure 7 CIS Master without shared clock ....................................................................................... 15
Figure 8 SLVS-EC Hierarchical Structure ....................................................................................... 16
Figure 9 Example of Single Stream Frame Format.......................................................................... 19
Figure 10 Example Frame Format and Control Sequence for Initialization .................................... 20
Figure 11 Example Frame Format and Control Sequence for Standby ............................................ 21
Figure 12 Example Frame Format and Control Sequence for Mode Change .................................. 22
Figure 13 Example Sequence of Lane Num Change (1 to 4)........................................................... 23
