目 录
论文总页数 26 页
1 绪论..................................................................................................................................................1
1.1 课题研究背景.......................................................................................................................1
1.2 课题研究现状.......................................................................................................................1
1.3 课题研究意义.......................................................................................................................1
1.4 课题实现手段.......................................................................................................................2
1.5 本文章节安排.......................................................................................................................2
2 相关理论研究..................................................................................................................................2
2.1 数字传输系统.......................................................................................................................2
2.2 数字复接技术.......................................................................................................................3
2.2.1 数字复接发展和原理................................................................................................3
2.2.3 数字复接方式及方法................................................................................................4
2.2.4 数字复接的系列标准................................................................................................5
2.3 码速调整技术.......................................................................................................................6
2.3.1 码速调整原理............................................................................................................6
2.3.2 码速调整帧结构........................................................................................................7
3 课题研究工具..................................................................................................................................8
3.1 Verilog HDL 硬件描述语言................................................................................................8
3.2 FPGA 硬件载体....................................................................................................................8
3.2 Quartus II 开发平台..............................................................................................................9
4 数字分接复用器的设计..................................................................................................................9
4.1 数字分接器的设计.............................................................................................................10
4.1.1 帧捕获模块..............................................................................................................10
4.1.2 串并转换模块..........................................................................................................12
4.1.3 码速调整模块..........................................................................................................13
4.1.4 仿真结果分析..........................................................................................................17
4.2 数字复用器的设计.............................................................................................................17
4.2.1 码速调整模块..........................................................................................................18
4.2.2 并串转换模块..........................................................................................................20
4.2.3 帧头插入模块..........................................................................................................20
4.2.4 仿真结果分析..........................................................................................................21
5 设计中遇到的问题........................................................................................................................22
5.1 信号的时延.........................................................................................................................22
5.2 毛刺的产生及消除.............................................................................................................22
5.3 Verilog HDL 的编译和调试..............................................................................................22
总 结..................................................................................................................................................23
参考文献...........................................................................................................................................24
