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TMS320F28004x-技术手册.pdf
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TMS320F28004x-技术手册.pdf
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TMS320F28004x Real-Time
Microcontrollers
Technical Reference Manual
Literature Number: SPRUI33D
NOVEMBER 2015 – REVISED SEPTEMBER 2020
Read This First.........................................................................................................................................................................69
About This Manual................................................................................................................................................................. 69
Notational Conventions.......................................................................................................................................................... 69
Glossary................................................................................................................................................................................. 69
Related Documentation From Texas Instruments.................................................................................................................. 69
Support Resources................................................................................................................................................................ 69
Trademarks............................................................................................................................................................................ 70
1 C2000™ Microcontrollers Software Support......................................................................................................................71
1.1 Introduction...................................................................................................................................................................... 72
1.2 C2000Ware Structure.......................................................................................................................................................72
1.3 Documentation................................................................................................................................................................. 72
1.4 Devices............................................................................................................................................................................ 72
1.5 Libraries........................................................................................................................................................................... 72
1.6 Code Composer Studio™ Integrated Development Environment (IDE).......................................................................... 73
1.7 PinMUX Tool.................................................................................................................................................................... 73
2 C28x Processor.....................................................................................................................................................................75
2.1 Introduction...................................................................................................................................................................... 76
2.2 Features........................................................................................................................................................................... 76
2.3 Floating-Point Unit............................................................................................................................................................76
2.4 Trigonometric Math Unit................................................................................................................................................... 76
2.5 Viterbi, Complex Math and CRC Unit (VCU)....................................................................................................................77
2.6 VCRC Unit........................................................................................................................................................................78
3 System Control and Interrupts............................................................................................................................................ 79
3.1 Introduction...................................................................................................................................................................... 80
3.2 Power Management......................................................................................................................................................... 80
3.2.1 Internal 1.2-V Switching Regulator (DC-DC)............................................................................................................. 80
3.3 Device Identification and Configuration Registers........................................................................................................... 81
3.4 Resets.............................................................................................................................................................................. 81
3.4.1 Reset Sources........................................................................................................................................................... 81
3.4.2 External Reset (
XRS)................................................................................................................................................ 82
3.4.3 Power-On Reset (POR).............................................................................................................................................82
3.4.4 Debugger Reset (SYSRS).........................................................................................................................................82
3.4.5 Watchdog Reset (WDRS)..........................................................................................................................................82
3.4.6 NMI Watchdog Reset (
NMIWDRS)............................................................................................................................82
3.4.7 DCSM Safe Code Copy Reset (SCCRESET)........................................................................................................... 83
3.5 Peripheral Interrupts.........................................................................................................................................................83
3.5.1 Interrupt Concepts..................................................................................................................................................... 83
3.5.2 Interrupt Architecture................................................................................................................................................. 83
3.5.3 Interrupt Entry Sequence...........................................................................................................................................84
3.5.4 Configuring and Using Interrupts...............................................................................................................................85
3.5.5 PIE Channel Mapping................................................................................................................................................87
3.5.6 Vector Tables............................................................................................................................................................. 89
3.6 Exceptions and Non-Maskable Interrupts........................................................................................................................ 95
3.6.1 Configuring and Using NMIs......................................................................................................................................95
3.6.2 Emulation Considerations..........................................................................................................................................95
3.6.3 NMI Sources..............................................................................................................................................................95
3.6.4 Illegal Instruction Trap (ITRAP)................................................................................................................................. 96
3.6.5 Error Pin.................................................................................................................................................................... 96
3.7 Clocking........................................................................................................................................................................... 97
Table of Contents
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SPRUI33D – NOVEMBER 2015 – REVISED SEPTEMBER 2020
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TMS320F28004x Real-Time Microcontrollers 3
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3.7.1 Clock Sources........................................................................................................................................................... 98
3.7.2 Derived Clocks........................................................................................................................................................ 100
3.7.3 Device Clock Domains............................................................................................................................................ 101
3.7.4 XCLKOUT................................................................................................................................................................102
3.7.5 Clock Connectivity................................................................................................................................................... 102
3.7.6 Clock Source and PLL Setup.................................................................................................................................. 103
3.7.7 Using an External Crystal or Resonator.................................................................................................................. 104
3.7.8 Using an External Oscillator.................................................................................................................................... 104
3.7.9 Choosing PLL Settings............................................................................................................................................ 104
3.7.10 System Clock Setup.............................................................................................................................................. 105
3.7.11 Clock Configuration Examples...............................................................................................................................105
3.7.12 Missing Clock Detection........................................................................................................................................ 106
3.8 32-Bit CPU Timers 0/1/2................................................................................................................................................ 107
3.9 Watchdog Timer............................................................................................................................................................. 108
3.9.1 Servicing the Watchdog Timer.................................................................................................................................109
3.9.2 Minimum Window Check......................................................................................................................................... 109
3.9.3 Watchdog Reset or Watchdog Interrupt Mode.........................................................................................................110
3.9.4 Watchdog Operation in Low Power Modes..............................................................................................................110
3.9.5 Emulation Considerations........................................................................................................................................110
3.10 Low Power Modes........................................................................................................................................................ 111
3.10.1 IDLE....................................................................................................................................................................... 111
3.10.2 Guidelines on Software Emulation of STANDBY Mode......................................................................................... 111
3.10.3 HALT...................................................................................................................................................................... 112
3.10.4 Flash Power-down Considerations........................................................................................................................ 113
3.11 Memory Controller Module........................................................................................................................................... 114
3.11.1 Functional Description............................................................................................................................................114
3.12 Flash and OTP Memory............................................................................................................................................... 121
3.12.1 Features................................................................................................................................................................ 121
3.12.2 Flash Tools............................................................................................................................................................ 121
3.12.3 Default Flash Configuration................................................................................................................................... 122
3.12.4 Flash Bank, OTP and Pump..................................................................................................................................122
3.12.5 Flash Module Controller (FMC)............................................................................................................................. 122
3.12.6 Flash and OTP and Wakeup Power-Down Modes................................................................................................ 123
3.12.7 Flash and OTP Performance.................................................................................................................................124
3.12.8 Flash Access Interface.......................................................................................................................................... 125
3.12.9 Erase/Program Flash.............................................................................................................................................127
3.12.10 Error Correction Code (ECC) Protection............................................................................................................. 128
3.12.11 Reserved Locations Within Flash and OTP.........................................................................................................132
3.12.12 Procedure to Change the Flash Control Registers..............................................................................................132
3.13 Dual Code Security Module (DCSM)........................................................................................................................... 133
3.13.1 Functional Description........................................................................................................................................... 133
3.13.2 C Code Example to Get Zone Select Block Addr for Zone1 in BANK0................................................................. 141
3.13.3 Flash and OTP Erase/Program............................................................................................................................. 141
3.13.4 Safe Copy Code.................................................................................................................................................... 141
3.13.5 SafeCRC............................................................................................................................................................... 142
3.13.6 CSM Impact on Other On-Chip Resources........................................................................................................... 142
3.13.7 Incorporating Code Security in User Applications................................................................................................. 144
3.14 System Control Registers............................................................................................................................................ 149
3.14.1 System Control Base Address Table..................................................................................................................... 149
3.14.2 ACCESS_PROTECTION_REGS Registers..........................................................................................................150
3.14.3 CLK_CFG_REGS Registers..................................................................................................................................173
3.14.4 CPU_SYS_REGS Registers................................................................................................................................. 189
3.14.5 CPUTIMER_REGS Registers............................................................................................................................... 226
3.14.6 DCSM_BANK0_Z1_REGS Registers....................................................................................................................233
3.14.7 DCSM_BANK0_Z2_REGS Registers....................................................................................................................258
3.14.8 DCSM_BANK1_Z1_REGS Registers....................................................................................................................278
3.14.9 DCSM_BANK1_Z2_REGS Registers....................................................................................................................288
3.14.10 DCSM_COMMON_REGS Registers...................................................................................................................298
3.14.11 DEV_CFG_REGS Registers................................................................................................................................311
3.14.12 DMA_CLA_SRC_SEL_REGS Registers.............................................................................................................339
Table of Contents
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4 TMS320F28004x Real-Time Microcontrollers SPRUI33D – NOVEMBER 2015 – REVISED SEPTEMBER 2020
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Copyright © 2020 Texas Instruments Incorporated
3.14.13 FLASH_CTRL_REGS Registers......................................................................................................................... 346
3.14.14 FLASH_ECC_REGS Registers........................................................................................................................... 356
3.14.15 MEM_CFG_REGS Registers.............................................................................................................................. 379
3.14.16 MEMORY_ERROR_REGS Registers................................................................................................................. 425
3.14.17 NMI_INTRUPT_REGS Registers........................................................................................................................ 443
3.14.18 PERIPH_AC_REGS Registers............................................................................................................................452
3.14.19 PIE_CTRL_REGS Registers............................................................................................................................... 506
3.14.20 UID_REGS Registers.......................................................................................................................................... 546
3.14.21 WD_REGS Registers.......................................................................................................................................... 555
3.14.22 XINT_REGS Registers........................................................................................................................................ 562
3.14.23 Register to Driverlib Function Mapping............................................................................................................... 571
4 ROM Code and Peripheral Booting...................................................................................................................................589
4.1 Introduction.................................................................................................................................................................... 590
4.2 Device Boot Sequence...................................................................................................................................................590
4.3 Device Boot Modes........................................................................................................................................................ 591
4.3.1 Configuring Alternate Boot Mode Pins.................................................................................................................... 592
4.3.2 Configuring Alternate Boot Mode Options............................................................................................................... 593
4.3.3 Boot Mode Example Use Cases..............................................................................................................................593
4.4 Device Boot Flow Diagrams...........................................................................................................................................594
4.4.1 Emulation Boot Flow Diagram................................................................................................................................. 596
4.4.2 Standalone Boot Flow Diagram...............................................................................................................................597
4.5 Device Reset and Exception Handling...........................................................................................................................598
4.5.1 Reset Causes and Handling....................................................................................................................................598
4.5.2 Exceptions and Interrupts Handling.........................................................................................................................598
4.6 Boot ROM Description................................................................................................................................................... 599
4.6.1 Boot ROM Registers................................................................................................................................................599
4.6.2 Boot ROM User OTP...............................................................................................................................................599
4.6.3 Entry Points............................................................................................................................................................. 600
4.6.4 Wait Points...............................................................................................................................................................600
4.6.5 Memory Maps..........................................................................................................................................................601
4.6.6 ROM Tables.............................................................................................................................................................603
4.6.7 Boot Modes............................................................................................................................................................. 605
4.6.8 Boot Data Stream Structure.................................................................................................................................... 618
4.6.9 GPIO Assignments.................................................................................................................................................. 620
4.6.10 Secure ROM Function APIs.................................................................................................................................. 623
4.6.11 DCSM Usage.........................................................................................................................................................624
4.6.12 Clock Initialization..................................................................................................................................................624
4.6.13 Boot Status Information......................................................................................................................................... 625
4.6.14 ROM Version......................................................................................................................................................... 626
4.7 The C2000 Hex Utility.................................................................................................................................................... 626
Example 4-2. HEX2000.exe Command Syntax................................................................................................................627
5 Control Law Accelerator (CLA)..........................................................................................................................................629
5.1 Introduction.................................................................................................................................................................... 630
5.1.1 Features.................................................................................................................................................................. 630
5.1.2 Block Diagram......................................................................................................................................................... 631
5.2 CLA Interface................................................................................................................................................................. 632
5.2.1 CLA Memory............................................................................................................................................................632
5.2.2 CLA Memory Bus.................................................................................................................................................... 633
5.2.3 Shared Peripherals and EALLOW Protection..........................................................................................................633
5.2.4 CLA Tasks and Interrupt Vectors............................................................................................................................. 634
5.2.5 CLA Software Interrupt to CPU............................................................................................................................... 637
5.3 CLA, DMA, and CPU Arbitration.................................................................................................................................... 637
5.3.1 CLA Message RAM................................................................................................................................................. 637
5.4 CLA Configuration and Debug....................................................................................................................................... 638
5.4.1 Building a CLA Application...................................................................................................................................... 638
5.4.2 Typical CLA Initialization Sequence........................................................................................................................ 638
5.4.3 Debugging CLA Code..............................................................................................................................................640
5.4.4 CLA Illegal Opcode Behavior.................................................................................................................................. 642
5.4.5 Resetting the CLA................................................................................................................................................... 642
5.5 Pipeline.......................................................................................................................................................................... 642
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Table of Contents
SPRUI33D – NOVEMBER 2015 – REVISED SEPTEMBER 2020
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TMS320F28004x Real-Time Microcontrollers 5
Copyright © 2020 Texas Instruments Incorporated
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