icc2-flow-script.pdf

Optional -> BLUE

Steps -> YELLOW

Sub-Categories -> GREEN

#To create user define log file and invoke gui

icc2 –out <name.log> -gui

#Set CPU cores usage

set_host_options –max_cores 8

#Sanity Checks

get_design_checks #List all design checks

check_design –checks {dp_pre_floorplan pre_placement_stage

timing physical_constraints}

check_design –checks dp_pre_floorplan #issues related to design

planning before floorplanning

check_design –checks pre_placement_stage #atomic checks ->

design mismatch, scan chain, mv design, timing, rp constraints

DMM – Mismatch

#(TCK-012) Input port with no input delay specified

#Floating pins, Multi-driven inputs/ports, undriven i/o, pin direction

mismatches,

Library Integrity Check – perform consistency check b/w logical and physical library

 Cells with missing PG pins

 Cells dimensions not an integer multiple of its site

 Cells with missing LEF (MX2X1)

 Cells PG pins geometry

 Cells with missing direction

Timing

 Report_disable_timing (l-loop breaking, c-case_analysis, f-false net arc) # check for

which cell arc’s what flag are given

 Input port has no clock_relative delay

Design (LINT checks) – validate the entire design hierarchy

 Unconstrainted_endpoints (can be clock not reaching a cell or missing output delays

 Undriven Inputs

 Undriven Ouputs

 Unloaded Nets

 Nets connected to multiple pins on same cell

Track definitions are defined

report_timing: Reports the timing informations of the current design (WLM), by default the worst

setup path in each clock group.

report_qor:

Splits the design based on Scenario/Timing path group

 Cell Area – Combinational and Sequential cell count ,buff/inv area, Cell area

 Design Rules – total no of nets/violations, Max tran, Max cap violations

Report_qor –summary

 WNS, TNS, NVE for each scenarios

 Cell area

 Nets with DRC violations

It reports the statistics/QoR of the current design viz, it's timing info, cell count, details like

combinational and non- combinational elements, total area of the current design. This will also

reports any DRV's present.

report_constraint:

check_design –checks dp_pre_floorplan

# Tech file is correct

check_design –checks dp_pre_create_placement_abstract

# Checks is constraint (SDC, UPF) files is specified

check_design –checks dp_pre_block_shaping

# Checks if core area and block boundaries are valid

check_design –checks dp_pre_power_insertion

#Preferred metal layers are defined

#No preferred routing direction defined for layers

#Mega checks are dp_pre_floorplan pre_placement_stage,

pre_clock_tree_stage & pre_route_stage

#ZIC

set_app_options –name time.delay_calculation_style –value

zero_interconnect

report_timing –slack_lesser_than 0

report_qor –summary (WNS, TNS, NVE)

report_timing –report_by _scenarios “S1 S2 S3”

#Check Timing Constraints

current_mode $mode

report_exceptions

report_case_analysis

report_disable_timing

}

#Set metal layers and direction for design

set_ignored_layers -max_routing_layer M8 -min_routing_layer M2

#View->Assistants->Hierarchy Exploration (OR)

explore_logic_hierarchy –create_module_boundary

#Manually create voltage area for MV design

create_voltage_area –power_domain –region

set_voltage_area <PD_RISC_CORE> -is_fixed

#Automatic voltage area creation

shape_blocks

#define hard keep out margin (even for LS and ISOcells)