Configuration and Debug of Complex Clock Networks Using CCOpt
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Contents
Purpose ....................................................................................................................... 4
Audience ...................................................................................................................... 4
Terms .......................................................................................................................... 4
Introduction .................................................................................................................. 5
Accompanying Information .......................................................................................... 5
Preparing the Run ........................................................................................................ 6
Recommended configuration settings ...................................................................... 6
Main flow stages of CCOpt (and what can be debugged at each stage) .................. 8
Debug Techniques ..................................................................................................... 18
Basic checks .......................................................................................................... 18
Using the CCOpt clock tree debugger .................................................................... 19
Clock path tracing and cross probing design views ................................................ 24
Reporting commands ............................................................................................. 25
Using CCOpt properties to gain design insight ...................................................... 26
Architectural Clock Control and Sink Modification ..................................................... 28
Blocking datapath portions of the design from the clock network ........................... 28
Deliberate skewing of clock points ......................................................................... 28
Balancing disjoint clock trees ................................................................................. 29
Preventing balancing of slave clocks derived from a common master ................... 29
Managing complex control logic that should not be skewed .................................. 31
Maintaining similar skew on logic driving output pins ............................................. 32
Handling macros with clock feedthroughs .............................................................. 33
Disabling synthesis of certain clocks ...................................................................... 34
Preventing excess buffering ................................................................................... 35
Miscellaneous constraint and clock propagation issues ......................................... 37
Support ...................................................................................................................... 41
Feedback ................................................................................................................... 41
