没有合适的资源？快使用搜索试试~ 我知道了~

文库首页行业研究行业报告A Brief Introduction to SystemVerilog Instructor.pdf

A Brief Introduction to SystemVerilog Instructor.pdf

需积分: 5 0 下载量 63 浏览量 2024-05-11 14:40:53 上传评论收藏 981KB PDF 举报

温馨提示

试读

41页

A Brief Introduction to SystemVerilog Instructor

资源推荐

资源详情

资源评论

Spring 2015 :: CSE 502 – Computer Architecture

A Brief

Introduction to

SystemVerilog

Instructor: Nima Honarmand

(Slides adapted from Prof. Milder’s ESE-507 course)

Spring 2015 :: CSE 502 – Computer Architecture

First Things First

• Assume you are familiar with the basics of digital

logic design

– If not, you can read Appendix A of Hamacher et al.

• SystemVerilog is a superset of another HDL: Verilog

– Familiarity with Verilog (or even VHDL) helps a lot

• Useful SystemVerilog resources and tutorials on the

course project web page

– Including a link to a good Verilog tutorial

Spring 2015 :: CSE 502 – Computer Architecture

Hardware Description Languages

• Used for a variety of purposes in hardware design

– High-level behavioral modeling

– Register Transfer Level (RTL) behavioral modeling

– Gate and transistor level netlists

– Timing models for timing simulation

– Design verification and testbench development

– …

• Many different features to accommodate all of these

• We focus on RTL modeling for the course project

– Much simpler than designing with gates

– Still, helps you think like a hardware designer

Spring 2015 :: CSE 502 – Computer Architecture

HDLs vs. Programming Languages

• Have syntactically similar constructs:

– Data types, variables, assignments, if statements, loops, …

• But very different mentality and semantic model:

everything runs in parallel, unless specified otherwise

– Statement model hardware

– Hardware is inherently parallel

• Software programs are composed of subroutines(mostly)

– Subroutines call each other

– when in a callee, the caller’s execution is paused

• Hardware descriptions are composed of modules (mostly)

– A hierarchy of modules connected to each other

– Modules are active at the same time

Spring 2015 :: CSE 502 – Computer Architecture

Modules

• The basic building block in SystemVerilog

– Interfaces with outside using ports

– Ports are either input or output (for now)

module mymodule(a, b, c, f);

output f;

input a, b, c;

// Description goes here

endmodule

// alternatively

module mymodule(input a, b, c, output f);

// Description goes here

endmodule

all ports declared here

declare which

ports are inputs,

which are outputs

module name

剩余40页未读，继续阅读

评论收藏

内容反馈

资源评论

资源反馈

评论星级较低，若资源使用遇到问题可联系上传者，3个工作日内问题未解决可申请退款~

Neo的作战室

粉丝: 36
资源: 5

上传资源快速赚钱

我的内容管理展开

我的资源快来上传第一个资源

我的收益

登录查看自己的收益

我的积分登录查看自己的积分

我的C币登录后查看C币余额

我的收藏

我的下载

下载帮助

前往需求广场，查看用户热搜

A Brief Introduction to SystemVerilog Instructor.pdf

A Brief Introduction to Boosting.pdf

A brief introduction to weakly supervised learning.pdf

A Brief Introduction of ATM.pdf

[Java语言程序设计].(Introduction.to.Java.Programming,.Brief.Version,.8ed),.Liang,.文字版

A Brief Introduction To DSB.ppt

神经网络简介A Brief Introduction to Neural Networks

A Brief Introduction to Machine Learning for Engineers.pdf

A Brief Introduction to Boosting

A Brief Introduction to Sigma Delta Conversion.pdf

A Gentle Introduction to ROS .pdf

A brief introduction to MetaPost

Think OS: A Brief Introduction to Operating Systems

Chapter One A brief history of project management.pdf

UML.Distilled__A.Brief.Guide.to.the.Standard.Object.Modeling.Language

[Java语言程序设计].(Introduction.to.Java.Programming,.Brief.Version,.8ed).pdf

A brief Introduction to Neural Networks

UNECE ：Nuclear power brief_EN_0.pdf

A Brief Introduction to PySpark

相关实用应用程序（Windows可用）

免费可用的ChatGPT网页版.zip

ChatGPT使用总结：150个ChatGPT提示词模板（完整版）

chromedriver-win64.zip

全国计算机二级WPSoffice精选350道选择题题库（含答案）.pdf

李飞飞自传 我看见的世界 The World I see

农村公交与异构无人机协同配送优化

哈尔滨工业大学-ChatGPT调研报告-2023.3.6-94页.pdf

4个亲测好用的ChatGPT4渠道

基于LSTM的财务因子预测选股模型.zip

最新资源

李飞飞自传我看见的世界 The World I see