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### CY8C21123 PSoC® Programmable System-on-Chip™ 特性与功能详述 #### 引言 CY8C21123 是由 Cypress Semiconductor Corporation 开发的一款 PSoC（Programmable System-on-Chip）系列的可编程片上系统。该芯片具有强大的处理能力、灵活的内存配置以及先进的外围设备，适用于多种嵌入式应用领域。本文将详细介绍 CY8C21123 的主要特性及其应用潜力。 #### 强大的哈佛架构处理器 - **M8C 处理器**：CY8C21123 配备了一个 M8C 处理器，运行速度最高可达 24 MHz。这为复杂的运算任务提供了必要的计算能力。 - **低功耗**：即便在高速运行下，M8C 处理器也能够保持较低的功耗水平。 - **宽电压范围**：处理器支持的工作电压范围为 2.4V 至 5.25V，并且可以通过内置的开关模式泵 (SMP) 将工作电压降至 1.0V。 - **工业级温度范围**：芯片可以在 -40°C 至 +85°C 的温度范围内正常工作，适用于恶劣环境下的应用。 #### 先进的外围设备（PSoC 块） - **模拟型“E”PSoC 块**：每个模拟型“E”块提供两个带有数字模拟转换器 (DAC) 参考的比较器，以及一个单通道或双通道 10 位 8 通路模拟数字转换器 (ADC)。 - **数字 PSoC 块**： - 8 至 32 位定时器/计数器，以及 8 和 16 位脉冲宽度调制器 (PWM)。 - 循环冗余校验 (CRC) 和可编程路由逻辑 (PRS) 模块。 - **通信接口**：全双工 UART 接口，支持 SPI 主机或从机模式，可以连接到所有通用输入输出 (GPIO) 引脚。 - **复杂外围设备构建**：通过组合不同的 PSoC 块，可以构建出更复杂的外围设备，以满足特定的应用需求。 #### 灵活的片上内存配置 - **闪存存储**：4KB 的闪存程序存储空间，支持 50,000 次擦写周期。 - **静态随机存取存储器 (SRAM)**：256 字节的数据存储空间。 - **在系统串行编程 (ISSP)**：支持 ISSP 功能，便于软件更新和调试。 - **部分闪存更新**：可以只更新闪存中的部分数据，减少整个系统重新编程的时间。 - **保护模式**：提供了灵活的保护模式，以防止未经授权的访问。 - **EEPROM 模拟**：在闪存中模拟 EEPROM 功能，提供非易失性存储选项。 #### 完整的开发工具链 - **PSoC Designer™ 软件**：免费提供的开发软件，用于设计和配置 PSoC 设备。 - **集成电路仿真器 (ICE) 和编程器**：提供了全面的仿真功能和支持，便于开发和调试过程。 - **跟踪内存**：128 KB 的跟踪内存，用于记录执行过程中的关键信息。 #### 精确的可编程时钟源 - **主振荡器**：内部集成 ±5% 的 24/48 MHz 主振荡器，为系统提供精确的时间基准。 - **低速低功耗振荡器**：用于监视和睡眠功能，有助于降低整体功耗。 #### 可编程的引脚配置 - **GPIO 驱动能力**：所有 GPIO 引脚都支持 25 mA 拉电流和 10 mA 推电流。 - **驱动模式**：所有 GPIO 支持上拉、下拉、高阻态、强推拉和开漏驱动模式。 - **模拟输入**：多达八个 GPIO 可以配置为模拟输入。 - **中断配置**：所有 GPIO 都支持中断配置，以提高系统的响应速度。 #### 额外的系统资源 - **I²C 接口**：支持 I²C 主机、从机和多主机模式，最高频率可达 400 kHz。 - **看门狗和睡眠定时器**：用于监测系统状态并实现低功耗模式。 - **低压检测 (LVD)**：用户可根据需要配置 LVD。 - **集成监控电路**：用于监控电源电压和其他关键参数。 - **片上精密参考电压**：为模拟信号处理提供稳定的参考电压。 ### 结论 CY8C21123 作为一款高度集成的可编程系统芯片，不仅具备强大的处理能力和丰富的外围设备资源，还提供了灵活的内存配置选项以及全面的开发工具支持。这些特点使得 CY8C21123 成为多种嵌入式应用的理想选择，特别是在需要高性能、低功耗和灵活设计的应用场景中。

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CY8C21123/CY8C21223/CY8C21323

PSoC

Programmable System-on-Chip™

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-12022 Rev. *Z Revised January 14, 2015

PSoC

Programmable System-on-Chip

™

Features

■ Powerful Harvard-architecture processor:

❐ M8C processor speeds up to 24 MHz

❐ Low power at high speed

❐ Operating voltage: 2.4 V to 5.25 V

❐ Operating voltages down to 1.0 V using on-chip switch mode

pump (SMP)

❐ Industrial temperature range: –40 °C to +85 °C

■ Advanced peripherals (PSoC

blocks):

❐ Four analog type “E” PSoC blocks provide:

• Two comparators with digital to analog converter (DAC)

references

• Single or dual 10-Bit 8-to-1 analog to digital converter

(ADC)

❐ Four digital PSoC blocks provide:

• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width

modulators (PWMs)

• CRC and PRS modules

❐ Full duplex UART, SPI master or slave: Connectable to all

general-purpose I/O (GPIO) pins

❐ Complex peripherals by combining blocks

■ Flexible on-chip memory:

❐ 4 KB flash program storage 50,000 erase/write cycles

❐ 256 bytes SRAM data storage

❐ In-system serial programming (ISSP)

❐ Partial flash updates

❐ Flexible protection modes

❐ EEPROM emulation in flash

■ Complete development tools:

❐ Free development software (PSoC Designer™)

❐ Full-featured, in-circuit emulator (ICE) and programmer

❐ Full-speed emulation

❐ Complex breakpoint structure

❐ 128-KB trace memory

■ Precision, programmable clocking:

❐ Internal ±5% 24- / 48-MHz main oscillator

❐ Internal low-speed, low-power oscillator for watchdog and

sleep functionality

■ Programmable pin configurations:

❐ 25-mA sink, 10-mA source on all GPIOs

❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes

on all GPIOs

❐ Up to eight analog inputs on all GPIOs

❐ Configurable interrupt on all GPIOs

■ Additional system resources:

❐ I

C master, slave and multi-master to 400 kHz

❐ Watchdog and sleep timers

❐ User-configurable low-voltage detection (LVD)

❐ Integrated supervisory circuit

❐ On-chip precision voltage reference

Logic Block Diagram

DIGITAL SYSTEM

SRAM

System Bus

Interrupt

Controller

Sleep and

Watchdog

Clock Source s

(Includes IMO and ILO)

Global Digital Interconnect

Global Analog Interconnect

PSoC

CORE

CPU Core

(M8C)

SROM Flash

I2C

Internal

Voltage

Ref .

Digital

Cloc ks

POR and LVD

System Resets

SYSTEM RESOURCES

ANALOG SYSTEM

Analog

Ref .

Por t 1 Por t 0

Digital

PSoC Block

Array

Analog

PSoC Block

Array

Sw itch

Mode

Pump

Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above 70 °C),

frequency tolerance deviates from ±2.5% to ±5%. For information on silicon errata, see “Errata” on page 42.

CY8C21123/CY8C21223/CY8C21323

Document Number: 38-12022 Rev. *Z Page 2 of 47

Contents

PSoC Functional Overview ..............................................3

PSoC Core ..................................................................3

Digital System .............................................................3

Analog System ............................................................4

Additional System Resources .....................................4

PSoC Device Characteristics ......................................5

Getting Started ..................................................................5

Application Notes ........................................................5

Development Kits ........................................................5

Training .......................................................................5

CYPros Consultants ....................................................5

Solutions Library ..........................................................5

Technical Support .......................................................5

Development Tool Selection ...........................................6

Software ......................................................................6

Designing with PSoC Designer .......................................7

Select Components .....................................................7

Configure Components ...............................................7

Organize and Connect ................................................7

Generate, Verify, and Debug .......................................7

Pin Information .................................................................8

8-Pin Part Pinout .........................................................8

16-Pin Part Pinout .......................................................8

20-Pin Part Pinout .....................................................10

24-Pin Part Pinout .....................................................11

Electrical Specifications ................................................16

Absolute Maximum Ratings .......................................16

Operating Temperature ............................................17

DC Electrical Characteristics .....................................17

AC Electrical Characteristics .....................................23

Packaging Information ...................................................31

Packaging Dimensions ..............................................31

Thermal Impedances ................................................34

Solder Reflow Specifications .....................................34

Ordering Information ......................................................35

Ordering Code Definitions ........................................35

Acronyms ........................................................................36

Acronyms Used .........................................................36

Reference Documents ....................................................36

Document Conventions .................................................37

Units of Measure .......................................................37

Numeric Conventions ................................................37

Glossary ..........................................................................37

Errata ...............................................................................42

Part Numbers Affected ..............................................42

CY8C21123 Qualification Status ...............................42

CY8C21123 Errata Summary .................................... 42

Document History Page .................................................44

Sales, Solutions, and Legal Information ......................47

Worldwide Sales and Design Support ....................... 47

Products ....................................................................47

PSoC® Solutions ......................................................47

Cypress Developer Community .................................47

Technical Support .....................................................47

CY8C21123/CY8C21223/CY8C21323

Document Number: 38-12022 Rev. *Z Page 3 of 47

PSoC Functional Overview

The PSoC family consists of many programmable

system-on-chip controller devices. These devices are designed

to replace multiple traditional MCU-based system components

with a low cost single-chip programmable component. A PSoC

device includes configurable blocks of analog and digital logic,

and programmable interconnect. This architecture allows you to

create customized peripheral configurations, to match the

requirements of each individual application. Additionally, a fast

CPU, Flash program memory, SRAM data memory, and

configurable I/O are included in a range of convenient pinouts.

The PSoC architecture, as shown in Figure 1, consists of four

main areas: the Core, the System Resources, the Digital

System, and the Analog System. Configurable global bus

resources allow the combining of all device resources into a

complete custom system. Each PSoC device includes four digital

blocks. Depending on the PSoC package, up to two analog

comparators and up to 16 GPIO are also included. The GPIO

provide access to the global digital and analog interconnects.

PSoC Core

The PSoC Core is a powerful engine that supports a rich

instruction set. It encompasses SRAM for data storage, an

interrupt controller, sleep and watchdog timers, and internal main

oscillator (IMO), and internal low-speed oscillator (ILO). The

CPU core, called the M8C, is a powerful processor with speeds

up to 24 MHz. The M8C is a four MIPS 8-bit Harvard-architecture

microprocessor.

System Resources provide additional capability, such as digital

clocks or I

C functionality for implementing an I

C master, slave,

MultiMaster, an internal voltage reference that provides an

absolute value of 1.3 V to a number of PSoC subsystems, an

SMP that generates normal operating voltages off a single

battery cell, and various system resets supported by the M8C.

The digital system consists of an array of digital PSoC blocks,

which can be configured into any number of digital peripherals.

The digital blocks can be connected to the GPIO through a series

of global bus that can route any signal to any pin. This frees

designs from the constraints of a fixed peripheral controller.

The analog system consists of four analog PSoC blocks,

supporting comparators and analog-to-digital conversion up to

10 bits of precision.

Digital System

The digital system consists of four digital PSoC blocks. Each

block is an 8-bit resource that can be used alone or combined

with other blocks to form 8, 16, 24, and 32-bit peripherals, which

are called user modules. Digital peripheral configurations

include:

■ PWMs (8- and 16-bit)

■ PWMs with dead band (8- and 16-bit)

■ Counters (8- to 32-bit)

■ Timers (8- to 32-bit)

■ UART 8-bit with selectable parity (up to two)

■ SPI master and slave

■ I

C slave, master, multi-master (one available as a system

resource)

■ Cyclical redundancy checker/generator (8-bit)

■ IrDA (up to two)

■ Pseudo random sequence generators (8- to 32-bit)

The digital blocks can be connected to any GPIO through a

series of global bus that can route any signal to any pin. The

busses also allow for signal multiplexing and performing logic

operations. This configurability frees your designs from the

constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of

blocks varies by PSoC device family. This provides an optimum

choice of system resources for your application. Family

resources are shown in Table 1 on page 5.

Figure 1. Digital System Block Diagram

DIGITAL SYSTEM

To System Bus

Di gi ta l P S oC Bl o ck Arr a y

To Anal og

System

Row Input

Configuration

Row Output

Configuration

Row 0

DBB00 DBB01 DCB02 DCB03

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]

Global Digital

Interconnect

Port 1

Port 0

CY8C21123/CY8C21223/CY8C21323

Document Number: 38-12022 Rev. *Z Page 4 of 47

Analog System

The analog system consists of four configurable blocks to allow

creation of complex analog signal flows. Analog peripherals are

very flexible and may be customized to support specific

application requirements. Some of the more common PSoC

analog functions (most available as user modules) are:

■ Analog-to-digital converters (single or dual, with 8-bit or 10-bit

resolution)

■ Pin-to-pin comparators (one)

■ Single-ended comparators (up to 2) with absolute (1.3 V)

reference or 8-bit DAC reference

■ 1.3 V reference (as a system resource)

In most PSoC devices, analog blocks are provided in columns of

three, which includes one CT (continuous time) and two SC

(switched capacitor) blocks. The CY8C21x23 devices provide

limited functionality Type “E” analog blocks. Each column

contains one CT block and one SC block.

The number of blocks on the device family is listed in Table 1 on

page 5.

Figure 2. CY8C21x23 Analog System Block Diagram

Additional System Resources

System resources, some of which listed in the previous sections,

provide additional capability useful to complete systems.

Additional resources include a switch mode pump, low voltage

detection, and power on reset. The merits of each system

resource are.

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks can be routed

to both the digital and analog systems. Additional clocks can

be generated using digital PSoC blocks as clock dividers.

■ The I

C module provides 100 and 400 kHz communication over

two wires. Slave, master, and multi-master modes are all

supported.

■ LVD interrupts can signal the application of falling voltage

levels, while the advanced POR (power on reset) circuit

eliminates the need for a system supervisor.

■ An internal 1.3 V voltage reference provides an absolute

reference for the analog system, including ADCs and DACs.

■ An integrated switch mode pump (SMP) generates normal

operating voltages from a single 1.2 V battery cell, providing a

low cost boost converter.

ACOL1M UX

ACE00 ACE01

Array

Array Input

Configuration

ACI0[1:0] ACI1[1:0]

ASE10 ASE11

CY8C21123/CY8C21223/CY8C21323

Document Number: 38-12022 Rev. *Z Page 5 of 47

PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or 4

analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is

highlighted.

Getting Started

The quickest way to understand PSoC silicon is to read this

datasheet and then use the PSoC Designer Integrated Devel-

opment Environment (IDE). This datasheet is an overview of the

PSoC integrated circuit and presents specific pin, register, and

electrical specifications.

For in depth information, along with detailed programming

details, see the Technical Reference Manual for this PSoC

device.

For up to date ordering, packaging, and electrical specification

information, see the latest PSoC device datasheets on the web

at http://www.cypress.com.

Application Notes

Application notes are an excellent introduction to the wide variety

of possible PSoC designs. They can be found at

http://www.cypress.com.

Development Kits

PSoC Development Kits are available online from Cypress at

http://www.cypress.com and through a growing number of

regional and global distributors, which include Arrow, Avnet,

Digi-Key, Farnell, Future Electronics, and Newark.

Training

Free PSoC technical training (on demand, webinars, and

workshops) is available online at http://www.cypress.com. The

training covers a wide variety of topics and skill levels to assist

you in your designs.

CYPros Consultants

Certified PSoC Consultants offer everything from technical

assistance to completed PSoC designs. To contact or become a

PSoC Consultant go to http://www.cypress.com and refer to

CYPros Consultants.

Solutions Library

Visit our growing library of solution focused designs at

http://www.cypress.com. Here you can find various application

designs that include firmware and hardware design files that

enable you to complete your designs quickly.

Technical Support

For assistance with technical issues, search KnowledgeBase

articles and forums at http://www.cypress.com. If you cannot find

an answer to your question, call technical support at

1-800-541-4736.

Table 1. PSoC Device Characteristics

PSoC Part

Number

Digital

I/O

Digital

Rows

Digital

Blocks

Analog

Inputs

Analog

Outputs

Analog

Columns

Analog

Blocks

SRAM

Size

Flash

Size

CY8C29x66 up to 64 4 16 up to 12 4 4 12 2 K 32 K

CY8C28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to

12 + 4

[1]

1 K 16 K

CY8C27x43 up to 44 2 8 up to 12 4 4 12 256 16 K

CY8C24x94 up to 56 1 4 up to 48 2 2 6 1 K 16 K

CY8C24x23A up to 24 1 4 up to 12 2 2 6 256 4 K

CY8C23x33 up to 26 1 4 up to 12 2 2 4 256 8 K

CY8C22x45 up to 38 2 8 up to 38 0 4 6

[1]

1 K 16 K

CY8C21x45 up to 24 1 4 up to 24 0 4 6

[1]

512 8 K

CY8C21x34 up to 28 1 4 up to 28 0 2 4

[1]

512 8 K

CY8C21x23 up to 16 1 4 up to 8 0 2 4

[1]

256 4 K

CY8C20x34 up to 28 0 0 up to 28 0 0 3

[1,2]

512 8 K

CY8C20xx6 up to 36 0 0 up to 36 0 0 3

[1,2]

up to

2 K

up to

32 K

Notes

1. Limited analog functionality.

2. Two analog blocks and one CapSense

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