Lontium Semiconductor
LT8619C_Register_List_Preliminary
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LONTIUM SEMICONDUCTOR CORPORATION
ClearedEdge
TM
Technology
LT8619C
HDMI To TTL/LVDS Converter
Register List
We produce mixed-signal products for a better digital world!
Lontium Semiconductor
LT8619C_Register_List_Preliminary
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Revision History
Version Owner Content Date
Preliminary DS.Ren Initial Release 08/11/2016
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LT8619C_Register_List_Preliminary
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Device Address: 0x64 Offset Address: 0x6000
Bits Name Description Access Default
7:0 CHIP_ID[23:16] RO 0x16
Default: 0x16
Device Address: 0x64 Offset Address: 0x6001
Bits Name Description Access Default
7:0 CHIP_ID[15:8] RO 0x04
Default: 0x04
Device Address: 0x64 Offset Address: 0x6002
Bits Name Description Access Default
7:0 CHIP_ID[7:0] RO 0xB0
Default: 0xB0
Device Address: 0x64 Offset Address: 0x6003
Bits Name Description Access Default
7:4 RESERVED RO 0xE
3:0 ECO_VER_DEC[3:0] Reserved. RO 0x0
Default: 0xE0
Device Address: 0x64 Offset Address: 0x6004
Bits Name Description Access Default
7
RGD_GAT_ANA_REG
_SYS_CLK_EN
Analog register clock enable(Address
range:0x6080-0x60FE).
RW 0x1
6
RGD_GAT_BIM_REG
_SYS_CLK_EN
Control register clock enable(Address
range:0x6010-0x607F).
RW 0x1
5
RGD_GAT_HDMI_RE
G_SYS_CLK_EN
HDMI register clock enable(Address
range:0x8000-0x809F).
RW 0x1
4
RGD_GAT_HDCP_RE
G_SYS_CLK_EN
HDCP register clock enable(Address
range:0x80A0-0x80CF).
RW 0x1
3:2 RESERVED RW 0x0
1
RGD_GAT_LVDSPLL_
LOCK_CLK_EN
LVDS PLL lock detect module clock enable.
RW 0x0
0
RGD_GAT_GPIO_TES
T_CLK_EN
GPIO FT test module clock enable.
RW 0x0
Default: 0xF0
Device Address: 0x64 Offset Address: 0x6005
Bits Name Description Access Default
7
RGD_GAT_HDCP_AU
TO_SYS_CLK_EN
HDCP control logic sys_clk clock enable.
RW 0x1
6
RGD_GAT_HDCP_KE
Y_SYS_CLK_EN
HDCP key management sys_clk clock enable.
RW 0x1
5
RGD_GAT_HDCP_RX
_PRTC_CLK_EN
HDCP RX protocol clock enable.
RW 0x1
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4
RGD_GAT_RXPLL_L
OCK_CLK_EN
RXPLL lock detect module clock enable.
RW 0x1
3
RGD_GAT_CDR_BW_
CLK_EN
CDR BW detect module clock enable.
RW 0x1
2
RGD_GAT_HDMIRX_
CLK_EN
HDMI RX video related clock enable.
RW 0x1
1
RGD_GAT_PKT_TMD
S_CLK_EN
HDMI RX de-packet mode tmds_clk clock enable.
RW 0x1
0
RGD_GAT_HDMIRX_
AUD_CLK_EN
HDMI RX audio related clock enable.
RW 0x1
Default: 0xFF
Device Address: 0x64 Offset Address: 0x6006
Bits Name Description Access Default
7
RGD_GAT_LVDS_CL
K_EN
LVDS TX controller module clock enable.
RW 0x0
6
RGD_GAT_BT_CLK_
EN
BT TX controller module clock enable.
RW 0x1
5
RGD_GAT_EDID_SYS
_CLK_EN
EDID shadow module sys_clk clock enable.
RW 0x1
4
RGD_GAT_ID_SYS_C
LK_EN
Dual-mode DP input mode id IIC slave module
sys_clk clock enable.
RW 0x0
3
RGD_GAT_CEC_SYS_
CLK_EN
CEC controller module sys_clk clock enable.
RW 0x0
2
RGD_GAT_VID_CHK
_SYS_CLK_EN
Video check module sys_clk clock enable.
RW 0x1
1
RGD_GAT_VID_CHK
_PIX_CLK_EN
Video check module pix_clk clock enable.
RW 0x1
0
RGD_GAT_INT_SYS_
CLK_EN
Interrupt process module sys_clk clock enable.
RW 0x1
Default: 0x67
Device Address: 0x64 Offset Address: 0x6007
Bits Name Description Access Default
7
RGD_GAT_CSC_PIX_
CLK_EN
CSC pix_clk clock enable(The bit is set to 1, forbid
set to 0).
RW 0x1
6
RGD_GAT_RGB2CBC
R_PIX_CLK_EN
RGB to YCbCr 444 converter clock enable.
RW 0x0
5
RGD_GAT_PBPR2CB
CR_PIX_CLK_EN
YPbPr to YCbCr converter clock enable.
RW 0x0
4
RGD_GAT_444TO422_
PIX_CLK_EN
YCbCr 444 to YCbCr 422 converter clock enable.
RW 0x0
3 RGD_GAT_422TO444_ YCbCr 422 to YCbCr 444 converter clock enable. RW 0x0
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PIX_CLK_EN
2
RGD_GAT_CBCR2RG
B_PIX_CLK_EN
YCbCr 444 to RGB converter clock enable.
RW 0x0
1
RGD_GAT_RGB_EXP
AND_PIX_CLK_EN
RGB range expand process clock enable.
RW 0x0
0
RGD_GAT_PTN_PIX_
CLK_EN
FT test pattern process module pix_clk clock
enable.
RW 0x0
Default: 0x80
Device Address: 0x64 Offset Address: 0x6008
Bits Name Description Access Default
7
RGD_ANA_REG_SW_
RST_N
Analog control(Address range:0x6080-0x60FE)
register module soft reset.
RW 0x1
6
RGD_BIM_REG_SW_
RST_N
Control(Address range:0x6010-0x607F) register
module soft reset.
RW 0x1
5
RGD_HDMI_REG_SW
_RST_N
HDMI RX control(Address range:0x8000-0x809F)
register module soft reset.
RW 0x1
4
RGD_HDCP_REG_SW
_RST_N
HDCP control(Address range:0x80A0-0x80CF)
register module soft reset.
RW 0x1
3:1 RESERVED RW 0x7
0
RGD_HDMIRX_CDR_
LOCK_RST_EN
Use cdr_lock hardware reset HDMI RX logic
enable.
RW 0x0
Default: 0xFE
Device Address: 0x64 Offset Address: 0x6009
Bits Name Description Access Default
7
RGD_HDMIRX_SW_R
ST_N
HDMI RX control logic soft reset.
RW 0x1
6
RGD_CDR_CTRL0_S
W_RST_N
HDMI RX CDR0 control logic soft reset.
RW 0x1
5
RGD_CDR_CTRL1_S
W_RST_N
HDMI RX CDR1 control logic soft reset.
RW 0x1
4
RGD_CDR_CTRL2_S
W_RST_N
HDMI RX CDR2 control logic soft reset.
RW 0x1
3
RGD_CDR_BW_SW_
RST_N
HDMI RX CDR BW detect logic soft reset.
RW 0x1
2
RGD_CDR_INDEX_S
W_RST_N
HDMI RX CDR index toggle control logic soft
reset.
RW 0x1
1
RGD_RXPLL_LOCK_
SW_RST_N
RXPLL lock detect control logic soft reset.
RW 0x1
0
RGD_RXPLL_LOCK_
RST_EN
Use RXPLL lock hardware reset PI,CDR and
HDMI RX control logic enable.
RW 0x1
Default: 0xFF
