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I2C总线数据手册,恩智浦半导体公司的UM1020。 I2C总线是由Philips公司开发的一种简单、双向二线制同步串行总线。它只需要两根线即可在连接于总线上的器件之间传送信息。 主器件用于启动总线传送数据,并产生时钟以开放传送的器件,此时任何被寻址的器件均被认为是从器件.在总线上主和从、发和收的关系不是恒定的,而取决于此时数据传送方向。如果主机要发送数据给从器件,则主机首先寻址从器件,然后主动发送数据至从器件,最后由主机终止数据传送;如果主机要接收从器件的数据,首先由主器件寻址从器件.然后主机接收从器件发送的数据,最后由主机终止接收过程。在这种情况下.主机负责产生定时时钟和终止数据传送。 I2C总线是公认的世界标准,由50多家公司生产超过1000个不同的地方实施的集成电路。此外,通用的i2c总线用于各种控制体系结构,如系统管理总线(SMBus),电源管理总线(PMBus),智能平台管理接口(IPMI),显示器数据通道(DDC)和高级电信计算架构(ATCA)。
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UM10204
I
2
C-bus specification and user manual
Rev. 4 — 13 February 2012 User manual
Document information
Info Content
Keywords I2C, I2C-bus, Standard-mode, Fast-mode, Fast-mode Plus, Fm+,
Ultra Fast-mode, UFm, High Speed, Hs, inter-IC, SDA, SCL, USDA, USCL
Abstract Philips Semiconductors (now NXP Semiconductors) developed a simple
bidirectional 2-wire bus for efficient inter-IC control. This bus is called the
Inter-IC or I
2
C-bus. Only two bus lines are required: a serial data line
(SDA) and a serial clock line (SCL). Serial, 8-bit oriented, bidirectional
data transfers can be made at up to 100 kbit/s in the Standard-mode, up to
400 kbit/s in the Fast-mode, up to 1 Mbit/s in the Fast-mode Plus (Fm+), or
up to 3.4 Mbit/s in the High-speed mode. The Ultra Fast-mode is a
uni-directional mode with data transfers of up to 5 Mbit/s.
UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 4 — 13 February 2012 2 of 64
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors
UM10204
I
2
C-bus specification and user manual
Revision history
Rev Date Description
v.4 20120213 Update user manual.
Modifications: • The format of this document has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Table “Document information”: added keywords “Ultra Fast-mode”, “UFm”, “USDA” and “USCL”
• New Section 3.1 created and (old) sections 3.1 to 3.17 are moved under this new section and
renumbered to Section 3.1.1
to Section 3.1.17.
• Section 3.1.12 “Reserved addresses”, added descriptive line below title of Table 3
• Added (new) Table 4 “Assigned manufacturer IDs”
• Added (new) Section 3.2 “Ultra Fast-mode I
2
C-bus protocol”
• Added (new) Section 4.6 “Display Data Channel (DDC)”
• added (new) Section 5.4 “Ultra Fast-mode”
• Table 9 “Characteristics of the SDA and SCL I/O stages”:
– symbol V
hys
: deleted condition “V
DD
> 2 V”; deleted condition “V
DD
< 2 V” and its values
– symbol V
OL3
replaced with symbol V
OL2
; added (new) Table note [3]
– parameter description for t
of
corrected from “output fall time from V
IHmax
to V
ILmax
” to “output
time from V
IHmin
to V
ILmax
”.
– t
of
Min values for Fast-mode and Fast-mode Plus are changed to “20 ns (V
DD
/5.5V)”
• Table 10 “Characteristics of the SDA and SCL bus lines for Standard, Fast, and Fast-mode Plus
I
2
C-bus devices
[1]
”:
– t
r
Min value for Fast-mode changed from “20 + 0.1C
b
ns” to “20 ns”
– t
f
Min values for Fast-mode and Fast-mode Plus are changed to “20 ns (V
DD
/5.5V)”
• Table 11 “Characteristics of the SDAH, SCLH, SDA and SCL I/O stages for Hs-mode I
2
C-bus
devices”: second Condition for V
OL
changed from “V
DD
< 2 V” to “V
DD
≤ 2V”
• Added (new) Section 6.3 “Ultra Fast-mode devices”.
• Section 7.1 “Pull-up resistor sizing”, third paragraph changed from “... is a function of the rise time
minimum (t
r
) ...” to “... is a function of the rise time maximum (t
r
) ...”
v.3 20070619 Many of today’s applications require longer buses and/or faster speeds. Fast-mode Plus was
introduced to meet this need by increasing drive strength by as much as 10× and increasing the data
rate to 1 Mbit/s while maintaining downward compatibility to Fast-mode and Standard-mode speeds
and software commands.
v2.1 2000 Version 2.1 of the I
2
C-bus specification
v2.0 1998 The I
2
C-bus has become a de facto world standard that is now implemented in over 1000 different ICs
and licensed to more than 50 companies. Many of today’s applications, however, require higher bus
speeds and lower supply voltages. This updated version of the I
2
C-bus specification meets those
requirements.
v1.0 1992 Version 1.0 of the I
2
C-bus specification
Original 1982 first release
UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 4 — 13 February 2012 3 of 64
NXP Semiconductors
UM10204
I
2
C-bus specification and user manual
1. Introduction
The I
2
C-bus is a de facto world standard that is now implemented in over 1000 different
ICs manufactured by more than 50 companies. Additionally, the versatile I
2
C-bus is used
in various control architectures such as System Management Bus (SMBus), Power
Management Bus (PMBus), Intelligent Platform Management Interface (IPMI), Display
Data Channel (DDC) and Advanced Telecom Computing Architecture (ATCA).
This document assists device and system designers to understand how the I
2
C-bus works
and implement a working application. Various operating modes are described. It contains
a comprehensive introduction to the I
2
C-bus data transfer, handshaking and bus
arbitration schemes. Detailed sections cover the timing and electrical specifications for the
I
2
C-bus in each of its operating modes.
Designers of I
2
C-compatible chips should use this document as a reference and ensure
that new devices meet all limits specified in this document. Designers of systems that
include I
2
C devices should review this document and also refer to individual component
data sheets.
2. I
2
C-bus features
In consumer electronics, telecommunications and industrial electronics, there are often
many similarities between seemingly unrelated designs. For example, nearly every
system includes:
• Some intelligent control, usually a single-chip microcontroller
• General-purpose circuits like LCD and LED drivers, remote I/O ports, RAM,
EEPROM, real-time clocks or A/D and D/A converters
• Application-oriented circuits such as digital tuning and signal processing circuits for
radio and video systems, temperature sensors, and smart cards
To exploit these similarities to the benefit of both systems designers and equipment
manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips
Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus
for efficient inter-IC control. This bus is called the Inter IC or I
2
C-bus. All I
2
C-bus
compatible devices incorporate an on-chip interface which allows them to communicate
directly with each other via the I
2
C-bus. This design concept solves the many interfacing
problems encountered when designing digital control circuits.
Here are some of the features of the I
2
C-bus:
• Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL).
• Each device connected to the bus is software addressable by a unique address and
simple master/slave relationships exist at all times; masters can operate as
master-transmitters or as master-receivers.
• It is a true multi-master bus including collision detection and arbitration to prevent data
corruption if two or more masters simultaneously initiate data transfer.
• Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in
the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in Fast-mode
Plus, or up to 3.4 Mbit/s in the High-speed mode.
UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 4 — 13 February 2012 4 of 64
NXP Semiconductors
UM10204
I
2
C-bus specification and user manual
• Serial, 8-bit oriented, unidirectional data transfers up to 5 Mbit/s in Ultra Fast-mode
• On-chip filtering rejects spikes on the bus data line to preserve data integrity.
• The number of ICs that can be connected to the same bus is limited only by a
maximum bus capacitance. More capacitance may be allowed under some
conditions. Refer to Section 7.2
.
Figure 1
shows an example of I
2
C-bus applications.
2.1 Designer benefits
I
2
C-bus compatible ICs allow a system design to progress rapidly directly from a
functional block diagram to a prototype. Moreover, since they ‘clip’ directly onto the
I
2
C-bus without any additional external interfacing, they allow a prototype system to be
modified or upgraded simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus.
Here are some of the features of I
2
C-bus compatible ICs that are particularly attractive to
designers:
• Functional blocks on the block diagram correspond with the actual ICs; designs
proceed rapidly from block diagram to final schematic.
• No need to design bus interfaces because the I
2
C-bus interface is already integrated
on-chip.
Fig 1. Example of I
2
C-bus applications
I
2
C
A/D or D/A
Converters
I
2
C
General Purpose
I/O Expanders
I
2
C
LED Controllers
V
DD4
I
2
C
Repeaters/
Hubs/Extenders
I
2
C
DIP Switches
V
DD5
I
2
C
Slave
V
DD0
V
DD1
PCA9541
I
2
C
Master Selector/
Demux
I
2
C
Multiplexers
and Switches
V
DD2
I
2
C Port
via HW or
Bit Banging
I
2
C
Bus Controllers
MCUs
8
MCUs
I
2
C
Serial EEPROMs
LCD Drivers
(with I
2
C)
I
2
C
Real Time Clock/
Calendars
V
DD3
I
2
C
Temperature
Sensors
Bridges
(with I
2
C)
SPI
UART
USB
002aac858
UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 4 — 13 February 2012 5 of 64
NXP Semiconductors
UM10204
I
2
C-bus specification and user manual
• Integrated addressing and data-transfer protocol allow systems to be completely
software-defined.
• The same IC types can often be used in many different applications.
• Design-time reduces as designers quickly become familiar with the frequently used
functional blocks represented by I
2
C-bus compatible ICs.
• ICs can be added to or removed from a system without affecting any other circuits on
the bus.
• Fault diagnosis and debugging are simple; malfunctions can be immediately traced.
• Software development time can be reduced by assembling a library of reusable
software modules.
In addition to these advantages, the CMOS ICs in the I
2
C-bus compatible range offer
designers special features which are particularly attractive for portable equipment and
battery-backed systems.
They all have:
• Extremely low current consumption
• High noise immunity
• Wide supply voltage range
• Wide operating temperature range.
2.2 Manufacturer benefits
I
2
C-bus compatible ICs not only assist designers, they also give a wide range of benefits
to equipment manufacturers because:
• The simple 2-wire serial I
2
C-bus minimizes interconnections so ICs have fewer pins
and there are not so many PCB tracks; result — smaller and less expensive PCBs.
• The completely integrated I
2
C-bus protocol eliminates the need for address decoders
and other ‘glue logic’.
• The multi-master capability of the I
2
C-bus allows rapid testing and alignment of
end-user equipment via external connections to an assembly line.
• The availability of I
2
C-bus compatible ICs in various leadless packages reduces
space requirements even more.
These are just some of the benefits. In addition, I
2
C-bus compatible ICs increase system
design flexibility by allowing simple construction of equipment variants and easy
upgrading to keep designs up-to-date. In this way, an entire family of equipment can be
developed around a basic model. Upgrades for new equipment, or enhanced-feature
models (that is, extended memory, remote control, etc.) can then be produced simply by
clipping the appropriate ICs onto the bus. If a larger ROM is needed, it is simply a matter
of selecting a microcontroller with a larger ROM from our comprehensive range. As new
ICs supersede older ones, it is easy to add new features to equipment or to increase its
performance by simply unclipping the outdated IC from the bus and clipping on its
successor.
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