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### SDRAM Controller Core n2cpu_nii51005：深入解析 #### 核心概述 SDRAM（同步动态随机存取存储器）在现代计算系统中扮演着至关重要的角色，尤其是在那些需要大量易失性内存且成本敏感的应用场景中。本章节将详细介绍Altera公司Quartus II Handbook Version 9.0 Volume 5中的SDRAM控制器核心n2cpu_nii51005。此控制器核心与Avalon接口集成，提供了连接外部SDRAM芯片的能力，并支持标准的SDRAM，如PC100规范所定义。 #### 功能描述 SDRAM控制器核心通过Avalon Memory-Mapped (Avalon-MM)接口与外部SDRAM进行通信。该核心允许设计者在其Altera设备内部创建自定义系统，这些系统能够轻松地与SDRAM芯片相连。SDRAM虽然价格相对较低，但需要复杂的控制逻辑来执行刷新操作、开行管理以及其他延迟和命令序列。SDRAM控制器核心能够处理所有这些协议需求，从而简化了设计过程。在内部，该核心表现为一个Avalon-MM从端口，对于其他Avalon-MM主外围设备而言，它呈现出线性内存的形式（扁平地址空间）。这种设计使得控制器可以高效地管理内存访问。 #### 设备支持 SDRAM控制器核心支持各种数据宽度（8位、16位、32位或64位），以及不同大小的内存和多个芯片选择信号。Avalon-MM接口具有延迟感知能力，这意味着读取传输可以被流水线化处理，从而提高性能。此外，该核心还可以选择性地与其它外部Avalon-MM三态设备共享地址和数据总线，这对于I/O引脚数量有限而需要连接多个内存芯片的系统来说是一项非常有用的功能。 #### 在SOPC Builder中的实例化 SDRAM控制器核心是SOPC Builder就绪的，可以轻松地集成到任何由SOPC Builder生成的系统中。这使得开发人员能够快速地将其添加到复杂的设计中，而无需额外编写复杂的接口代码。 #### 硬件仿真考虑为了确保设计的正确性和可靠性，在硬件实现之前进行仿真测试是非常重要的。本节讨论了在硬件仿真过程中需要注意的一些关键点，包括如何设置测试环境、如何配置SDRAM控制器核心及其外围设备，以及如何验证其功能是否符合预期。 #### 软件编程模型除了硬件方面之外，软件编程也是成功实现SDRAM控制器的关键因素之一。本节将介绍如何通过软件来访问和控制SDRAM控制器核心，包括如何初始化控制器、如何配置SDRAM的工作模式等。 #### 时钟、PLL和定时考虑时钟信号对于SDRAM控制器的正常工作至关重要。本节将探讨与SDRAM控制器相关的时钟、PLL（锁相环）和定时方面的问题，包括如何为SDRAM控制器提供稳定可靠的时钟源，以及如何解决由于时序偏差导致的问题。 #### 总结 SDRAM控制器核心n2cpu_nii51005是Altera公司提供的一个强大工具，旨在帮助设计者轻松地在FPGA中实现对SDRAM的有效管理。通过深入了解其功能特点和技术细节，设计者可以更好地利用这一资源来优化其系统的性能和效率。无论是对于初学者还是有经验的工程师来说，掌握这一核心都是十分有价值的。

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1. SDRAM Controller Core

Core Overview

The SDRAM controller core with Avalon

interface provides an Avalon

Memory-Mapped (Avalon-MM) interface to off-chip SDRAM. The SDRAM controller

allows designers to create custom systems in an Altera

device that connect easily to

SDRAM chips. The SDRAM controller supports standard SDRAM as described in the

PC100 specification.

SDRAM is commonly used in cost-sensitive applications requiring large amounts of

volatile memory. While SDRAM is relatively inexpensive, control logic is required to

perform refresh operations, open-row management, and other delays and command

sequences. The SDRAM controller connects to one or more SDRAM chips, and

handles all SDRAM protocol requirements. Internal to the device, the core presents an

Avalon-MM slave port that appears as linear memory (flat address space) to

Avalon-MM master peripherals.

The core can access SDRAM subsystems with various data widths (8, 16, 32, or

64 bits), various memory sizes, and multiple chip selects. The Avalon-MM interface is

latency-aware, allowing read transfers to be pipelined. The core can optionally share

its address and data buses with other off-chip Avalon-MM tri-state devices. This

feature is valuable in systems that have limited I/O pins, yet must connect to multiple

memory chips in addition to SDRAM.

The SDRAM controller core with Avalon interface is SOPC Builder-ready and

integrates easily into any SOPC Builder-generated system. This chapter contains the

following sections:

■ “Functional Description” on page 1–2

■ “Device Support” on page 1–5

■ “Instantiating the Core in SOPC Builder” on page 1–5

■ “Hardware Simulation Considerations” on page 1–7

■ “Software Programming Model” on page 1–10

■ “Clock, PLL and Timing Considerations” on page 1–10

NII51005-9.0.0

Chapter 1: SDRAM Controller Core 1–3

Functional Description

Off-Chip SDRAM Interface

The interface to the external SDRAM chip presents the signals defined by the PC100

standard. These signals must be connected externally to the SDRAM chip(s) through

I/O pins on the Altera device.

Signal Timing and Electrical Characteristics

The timing and sequencing of signals depends on the configuration of the core. The

hardware designer configures the core to match the SDRAM chip chosen for the

system. See “Instantiating the Core in SOPC Builder” on page 1–5 for details. The

electrical characteristics of the device pins depend on both the target device family

and the assignments made in the Quartus

II software. Some device families support

a wider range of electrical standards, and therefore are capable of interfacing with a

greater variety of SDRAM chips. For details, refer to the device handbook for the

target device family.

Synchronizing Clock and Data Signals

The clock for the SDRAM chip (SDRAM clock) must be driven at the same frequency

as the clock for the Avalon-MM interface on the SDRAM controller (controller clock).

As in all synchronous designs, you must ensure that address, data, and control signals

at the SDRAM pins are stable when a clock edge arrives. As shown in Figure 1–1, you

can use an on-chip phase-locked loop (PLL) to alleviate clock skew between the

SDRAM controller core and the SDRAM chip. At lower clock speeds, the PLL might

not be necessary. At higher clock rates, a PLL is necessary to ensure that the SDRAM

clock toggles only when signals are stable on the pins. The PLL block is not part of the

SDRAM controller core. If a PLL is necessary, you must instantiate it manually. You

can instantiate the PLL core interface, which is an SOPC Builder component, or

instantiate an ALTPLL megafunction outside the SOPC Builder system module.

If you use a PLL, you must tune the PLL to introduce a clock phase shift so that

SDRAM clock edges arrive after synchronous signals have stabilized. See “Clock, PLL

and Timing Considerations” on page 1–10 for details.

f For more information about instantiating a PLL in your SOPC Builder system, refer to

PLL Core chapter in volume 5 of the Quartus II Handbook. The Nios

II development

tools provide example hardware designs that use the SDRAM controller core in

conjunction with a PLL, which you can use as a reference for your custom designs.

The Nios II development tools are available free for download from www.altera.com.

Clock Enable (CKE) Not Supported

The SDRAM controller does not support clock-disable modes. The SDRAM controller

permanently asserts the CKE signal on the SDRAM.

Sharing Pins with Other Avalon-MM Tri-State Devices

If an Avalon-MM tri-state bridge is present in the SOPC Builder system, the SDRAM

controller core can share pins with the existing tri-state bridge. In this case, the core’s

addr, dq (data) and dqm (byte-enable) pins are shared with other devices connected

to the Avalon-MM tri-state bridge. This feature conserves I/O pins, which is valuable

in systems that have multiple external memory chips (for example, flash, SRAM, and

SDRAM), but too few pins to dedicate to the SDRAM chip. See “Performance

Considerations” for details about how pin sharing affects performance.

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