Datasheet for Telink TLSR8278
DS-TLSR8278-E7 3 Ver 0.8.3
0.8.2
• Chapter 1 Overview: Added the description of regulation compliance
• Section 1.1 Block Diagram: Removed extra "k" for 1 MB FLASH in Figure 1-1
• Section 1.2.2 RF Features: Updated the description for RX sensitivity, data unchanged
• Section 1.2.3 Features of Power Management Module: Updated power consumption for deep sleep
• Section 1.2.5 Flash Features: Removed firmware encryption related feature description
• Section 1.4 Ordering Information: Added "TLSR" to “8278” for the footnote MSL of Table 1-1
• Section 1.6 Pin Layout: Added PTA description to Table 1-3
• Section 3.3 Baseband: Revised the specification Bluetooth 5 to Bluetooth 5.1
• Section 7.1 GPIO: Updated the first sentence of Section 7.1 describing GPIO number
• Section 19.3 DC Characteristics: Added condition description, revised I
Deep1
, added data for deep
sleep with 32K RC in Table 19-3
• Section 19.4 AC Characteristics: Revised the frequency range, adjusted the column sequence of TX/
RX Performance of modes, revised co-channel rejection, in-band blocking rejection, image rejection
for RX performance of all modes, revised modulation 20 dB bandwidth for TX performance of all
modes, revised frequency offset tolerance for BLE 125 kbps and 500 kbps, placed EVM for IEEE
802.15.4 250 kbps under TX performance column, removed footnotes of all modes regarding RX
sensitivity level in Table 19-5; revised resolution for RSSI to ±1 in Table 19-7
0.8.3
• Cover: Updated keywords and removed VID info from brief
• Section 1.1 Block Diagram: Revised Figure 1-1
• Updated UID related information: Revised UID related description in Section 1.2.1 General Features,
removed related description in Section 2.1.2 Flash, updated the description in Section 2.1.3 E-Fuse
and added Section 2.1.4 Unique ID
• Section 1.2.1 General Features: Updated ECC description
• Section 1.2.3 Features of Power Management Module: Updated RX/TX current with DCDC
• Section 1.4 Ordering Information: Changed the column heading "Product Part No." to "Ordering
No." in Table 1-1 and removed the footnote MSL from Table 1-1
• Section 1.6 Pin Layout: Removed the note regarding PTA for Table 1-3; pin PC[1] other than PC[2]
can be multiplexed as audio_in, corrected Table 1-4; fixed the typo for antenna in Table 1-14, fixed
the typo of DECODEC in the title of Table 1-17, fixed the typo for DI, the I/O type of MDEC signal in
Table 1-17
• Section 2.1.1 SRAM/Register: Corrected the register address to 0x800000 ~ 0x83FFFF and added
SWM as the debugging interface
• Section 2.4 Reset: Removed RSVD from the description of register 0x60 [2] and register 0x62 [1] in
Table 2-4
• Section 2.5.2 Working Mode Switch: Corrected the cross-reference to Table 2-2 and corrected the
retention SRAM description
Version Change Description
