FPGA常用通信总线IIC Verilog代码

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Legal Partition Candidates ; +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ; seg7_lut ; 9 ; 4 ; 1 ; 4 ; 11 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; iic_wr ; 4 ; 0 ; 0 ; 0 ; 10 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+