FPGA USB 2.0 IP核工程

The USB 2.0 Function Project Page is: http://www.opencores.org/cores/usb/ To find out more about me (Rudolf Usselmann), please visit: http://www.asics.ws Directory Structure ------------------- [core_root] | +-doc Documentation | +-bench--+ Test Bench | +- verilog Verilog Sources | +-vhdl VHDL Sources | +-rtl----+ Core RTL Sources | +-verilog Verilog Sources | +-vhdl VHDL Sources | +-sim----+ | +-rtl_sim---+ Functional verification Directory | | +-bin Makefiles/Run Scripts | | +-run Working Directory | | | +-gate_sim--+ Functional & Timing Gate Level | | Verification Directory | +-bin Makefiles/Run Scripts | +-run Working Directory | +-lint--+ Lint Directory Tree | +-bin Makefiles/Run Scripts | +-run Working Directory | +-log Linter log & result files | +-syn---+ Synthesis Directory Tree | +-bin Synthesis Scripts | +-run Working Directory | +-log Synthesis log files | +-out Synthesis Output