The USB 2.0 Function Project Page is:
http://www.opencores.org/cores/usb/
To find out more about me (Rudolf Usselmann), please visit:
http://www.asics.ws
Directory Structure
-------------------
[core_root]
|
+-doc Documentation
|
+-bench--+ Test Bench
| +- verilog Verilog Sources
| +-vhdl VHDL Sources
|
+-rtl----+ Core RTL Sources
| +-verilog Verilog Sources
| +-vhdl VHDL Sources
|
+-sim----+
| +-rtl_sim---+ Functional verification Directory
| | +-bin Makefiles/Run Scripts
| | +-run Working Directory
| |
| +-gate_sim--+ Functional & Timing Gate Level
| | Verification Directory
| +-bin Makefiles/Run Scripts
| +-run Working Directory
|
+-lint--+ Lint Directory Tree
| +-bin Makefiles/Run Scripts
| +-run Working Directory
| +-log Linter log & result files
|
+-syn---+ Synthesis Directory Tree
| +-bin Synthesis Scripts
| +-run Working Directory
| +-log Synthesis log files
| +-out Synthesis Output
USB2.0的IP核（详细verilog源码和文档） (1).rar （65个子文件） 
usb_funct rtl verilog 
usbf_pe.v 27KB usbf_mem_arb.v 5KB usbf_crc5.v 4KB usbf_utmi_if.v 6KB usbf_pl.v 13KB usbf_wb.v 7KB usbf_pd.v 12KB usbf_ep_rf.v 12KB usbf_crc16.v 5KB usbf_pa.v 8KB CVS Entries 714B Repository 22B Root 13B usbf_defines.v 9KB usbf_ep_rf_dummy.v 5KB usbf_idma.v 12KB usbf_rf.v 49KB usbf_top.v 17KB usbf_utmi_ls.v 16KB CVS Entries 14B Repository 14B Root 13B sim rtl_sim bin CVS Entries 2B Repository 26B Root 13B run CVS Entries 2B Repository 26B Root 13B CVS Entries 20B Repository 22B Root 13B CVS Entries 14B Repository 14B Root 13B doc 
STATUS.txt 2KB
usb_doc.pdf 314KB CVS Entries 135B Repository 14B Root 13B README.txt 1KB bench verilog CVS Entries 2B Repository 24B Root 13B CVS Entries 14B Repository 16B Root 13B syn bin comp.dc 4KB read.dc 2KB design_spec.dc 741B CVS Entries 173B Repository 18B Root 13B lib_spec.dc 1KB log CVS Entries 2B Repository 18B Root 13B run CVS Entries 2B Repository 18B Root 13B out CVS Entries 2B Repository 18B Root 13B CVS Entries 40B Repository 14B Root 13B
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