TPS92691/-Q1具有轨到轨电流感测放大器的多拓扑LED驱动器，60V

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(V)

Efficiency (%)

8 9 10 11 12 13 14 15 16 17 18

100

D019

= 60 V, I

LED

= 300 mA

TPS92691-Q1

VIN LED+

LEDÅ

VIN

RT/SYNC

PWM

COMP

IADJ

IMON

AGND

PAD

VCC

GATE

PGND

OVP

DDRV

CSP

CSN

OV1

OV2

COMP

IMON

OUT

VCC

ADJ2

ADJ1

PWM

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSD68

TPS92691

TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

TPS92691/-Q1 具具有有轨轨到到轨轨电电流流感感测测放放大大器器的的多多拓拓扑扑 LED 驱驱动动器器

1 特特性性

• 宽输入电压范围：4.5V 至 65V

• 宽输出电压范围：2V 至 65V

• 低输入偏移轨到轨电流感测放大器

– 在 25°C 至 140°C 结温范围内，好于 ±3% 的发

光二极管 (LED) 电流精度

– 与高侧和低侧电流感测元件兼容

• 高阻抗模拟 LED 电流调节输入 (IADJ)，对比度高

于 15:1

• 使用集成的串联 N 通道调光驱动器接口时，具有超

过 1000:1 串联场效应管 (FET) 脉宽调制 (PWM)

调光比率

• 具有 LED 电流持续监视输出用于系统故障检测和

诊断

• 可编程开关频率以实现与外部时钟同步

• 可编程软启动和斜坡补偿

• 综合故障保护电路，包括电源电压 (VCC) 欠压锁定

(UVLO)、输出过压保护 (OVP)、逐周期开关电流限

制和热保护

• TPS92691-Q1：符合汽车类 Q100 1 级标准

2 应应用用

• TPS92691-Q1：汽车外部照明应用

• 建筑照明和通用照明应用

3 说说明明

TPS92691/-Q1 是一款通用 LED 控制器，支持一系列

升压或降压驱动器拓扑。该器件实现了固定频率峰值电

流模式控制技术，可编程开关频率、斜坡补偿和软启动

时序。其整合了高电压 (65V) 轨到轨电流感测放大

器，从而可使用高侧或低侧串联感测电阻直接测量

LED 电流。该放大器可用于实现低输入偏移电压且在

25°C 至 140°C 结温范围和 0 至 60V 输出共模电压范

围获得好于 ±3% 的 LED 电流精度。

可使用模拟或 PWM 调光技术单独调制 LED 电流。通

过在高阻抗模拟调整输入 (IADJ) 范围内将电压从

140mV 改变为 2.25V 可获得具有 15:1 范围的线性模

拟调光响应。通过将 PWM 输入引脚调制为所需的占

空比和频率实现 LED 电流的 PWM 调光。可使用可选

DDRV 栅极驱动器输出使串联 FET 调光功能获得高于

1000:1 的对比度。

TPS92691/-Q1 支持通过电流监视输出连续检查 LED

状态。这样就可以实现 LED 短路或开路检测和保护。

其他故障保护特性包括 VCC UVLO、输出过压保护

(OVP)、开关逐周期电流限制和热保护。

器器件件信信息息

(1)

器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））

TPS92691-Q1

TPS92691

HTSSOP (16) 5.10mm x 6.60mm

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

典典型型升升压压 LED 驱驱动动器器应应用用原原理理图图

效效率率与与输输出出电电压压之之间间的的关关系系

TPS92691

TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

目目录录

1 特特性性.......................................................................... 1

2 应应用用.......................................................................... 1

3 说说明明.......................................................................... 1

4 修修订订历历史史记记录录 ........................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 7

7 Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 16

8 Application and Implementation ........................ 17

8.1 Application Information............................................ 17

8.2 Typical Applications ................................................ 26

9 Power Supply Recommendations...................... 37

10 Layout................................................................... 37

10.1 Layout Guidelines ................................................. 37

10.2 Layout Example .................................................... 38

11 器器件件和和文文档档支支持持 ..................................................... 39

11.1 相关链接................................................................ 39

11.2 社区资源................................................................ 39

11.3 商标 ....................................................................... 39

11.4 静电放电警告......................................................... 39

11.5 Glossary................................................................ 39

12 机机械械、、封封装装和和可可订订购购信信息息....................................... 39

4 修修订订历历史史记记录录

日日期期修修订订版版本本注注释释

2015 年 12 月 * 首次发布。

Thermal

Pad

VIN

RT/SYNC

PWM

COMP

IADJ

IMON

AGND

VCC

GATE

PGND

OVP

DDRV

CSP

CSN

TPS92691

TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

5 Pin Configuration and Functions

PWP Package

16-Pin HTSSOP with PowerPAD™

Top View

Pin Functions

I/O DESCRIPTION

NO. NAME

1 VIN —

Input supply for the internal VCC regulator. Bypass with 100-nF capacitor to GND located close to the

controller.

2 SS I/O

Soft-start programming pin. Connect a capacitor to AGND to extend the start-up time. Switching can

be disabled by shorting the pin to GND.

3 RT/SYNC I/O

Oscillator frequency programming pin. Connect a resistor to AGND to set the switching frequency. The

internal oscillator can be synchronized by coupling an external clock pulse through 100-nF series

capacitor.

4 PWM I

PWM dimming input. Driving the pin below 2.3 V (typ), turns off switching, idles the oscillator,

disconnects the COMP pin, and sets DDRV output to ground. The input signal duty cycle controls the

average LED current through PWM dimming operation. Connect to VCC when not used for PWM

dimming.

5 COMP I/O

Transconductance error amplifier output. Connect compensation network to achieve desired closed-

loop response.

6 IADJ I

LED current reference input. Connecting pin to VCC with 100-kΩ series resistor sets internal reference

voltage to 2.42 V and the current sense threshold, V

(CSP-CSN)

to 172 mV. The pin can be modulated by

external voltage source from 0 V to 2.25 V to implement analog dimming.

7 IMON O

LED current report pin. The LED current sensed by CSP/CSN input is reported as V

IMON

= 14 × I

LED

. Bypass with a 1-nF ceramic capacitor to AGND.

8 AGND —

Analog ground. Return for the internal voltage reference and analog circuit. Connect to circuit ground,

GND, to complete return path.

9 CSN I

Current sense amplifier negative input (–). Connect directly to the negative node of LED current sense

resistor R

10 CSP I

Current sense amplifier positive input (+). Connect directly to the positive node of LED current sense

resistor R

11 DDRV O

Series dimming FET gate driver output. Connect to gate of external N-channel MOSFET or a level-shift

circuit with P-channel MOSFET to implement series FET PWM dimming.

12 OVP I

Hysteretic overvoltage protection input. Connect resistor divider from output voltage to set OVP

threshold and hysteresis.

13 PGND —

Power ground connection pin for internal N-channel MOSFET gate drivers. Connect to circuit ground,

GND, to complete return path.

14 IS I

Switch current sense input. Connected to the switch current sense resistor, R

, in the source of the N-

channel MOSFET.

15 GATE O N-channel MOSFET gate driver output. Connect to gate of external switching N-channel MOSFET.

16 VCC —

VCC bias supply pin. Locally decouple to PGND using a 2.2-µF to 4.7-µF ceramic capacitor located

close to the controller.

PowerPAD —

The AGND and PGND pin must be connected to the exposed PowerPAD for proper operation. This

PowerPAD must be connected to PCB ground plane using multiple vias for good thermal performance.

TPS92691

TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to AGND unless otherwise noted

(3) Continuous sustaining voltage

(4) All output pins are not specified to have an external voltage applied.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)(2)

MIN MAX UNIT

Input voltage

VIN, CSP, CSN –0.3 65 V

IADJ, IS, PWM, RT/SYNC –0.3 8.8 V

OVP, SS –0.3 5.5 V

CSP to CSN

(3)

, PGND –0.3 0.3 V

Output voltage

(4)

VCC, GATE, DDRV –0.3 8.8 V

COMP –0.3 5.0 V

Source current

IMON — 100 µA

GATE, DDRV (Pulsed <20 ns) — 500 mA

Sink current GATE, DDRV (Pulsed <20 ns) — 500 mA

Operating junction temperature, T

–40 140 °C

Storage temperature, T

stg

150 °C

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE UNIT

TPS92691-Q1 IN PWP (HTSSOP) PACKAGE

(ESD)

Electrostatic

discharge

Human-body model (HBM), per AEC Q100-002, all pins

(1)

±2000

Charged-device model (CDM), per AEC Q100-011

All pins except 1, 8, 9, and

±500

Pins 1, 8, 9, and 16 ±750

TPS92691 IN PWP (HTSSOP) PACKAGE

(ESD)

Electrostatic

discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

(2)

±2000

Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins

(3)

±500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VIN Supply input voltage 6.5 14 65 V

VIN, crank Supply input, battery crank voltage 4.5 V

CSP

, V

CSN

Current sense common mode 0 60 V

Switching frequency 80 700 kHz

SYNC

SYNC frequency 0.8 × ƒ

1.2 × ƒ

kHz

IADJ

Current reference voltage 0.14 V

IADJ(CLAMP)

Operating ambient temperature –40 125 °C

TPS92691

TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.4 Thermal Information

THERMAL METRIC

(1)

TPS92691/-Q1

UNITPWP (HTSSOP)

16 PINS

θJA

Junction-to-ambient thermal resistance 40.8 °C/W

θJC(top)

Junction-to-case (top) thermal resistance 26.1 °C/W

θJB

Junction-to-board thermal resistance 22.2 °C/W

Junction-to-top characterization parameter 0.8 °C/W

Junction-to-board characterization parameter 22.0 °C/W

θJC(bot)

Junction-to-case (bottom) thermal resistance 2.3 °C/W

(1) All voltages are with respect to AGND unless otherwise noted

6.5 Electrical Characteristics

= –40°C to 140°C, V

= 14 V, V

IADJ

= 2.2 V, C

VCC

= 1 µF, C

COMP

= 2.2 nF, R

= 100 mΩ, R

= 20 kΩ, V

PWM

= 5 V, no load

on GATE and DDRV (unless otherwise noted)

(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT VOLTAGE (VIN)

LDO dropout voltage I

= 20 mA, V

= 5 V 300 mV

BIAS SUPPLY (VCC)

CC(REG)

Regulation voltage No load 7.0 7.5 8.0 V

CC(UVLO)

Supply undervoltage protection

VCC rising threshold, V

= 8 V 4.1 4.35 V

VCC falling threshold, V

= 8 V 3.75 4.0 V

Hysteresis 100 mV

CC(LIMIT)

Supply current limit V

= 0 V 26 38 46 mA

CC(STBY)

Supply stand-by current V

PWM

= 0 V 1.8 2.1 mA

CC(SW)

Supply switching current V

= 7.5 V, C

GATE

= 1 nF 5.1 6.6 mA

OSCILLATOR (RT/SYNC)

Switching frequency

= 40 kΩ 165 200 230 kHz

= 20 kΩ 327 390 448 kHz

RT output voltage 1 V

SYNC

SYNC rising threshold V

RT/SYNC

rising 2.7 3.1 V

SYNC falling threshold V

RT/SYNC

falling 1.8 2 V

SYNC(MIN)

Minimum SYNC clock pulse width 100 ns

GATE DRIVER (GATE)

Gate driver high side resistance I

GATE

= –10 mA 5.4 11.2 Ω

Gate driver low side resistance I

GATE

= 10 mA 4.3 10.5 Ω

CURRENT SENSE (IS)

IS(LIMIT)

Current limit threshold 497 525 550 mV

IS(BLANK)

Leading edge blanking time 103 150 188 ns

IS(FAULT)

Current limit fault time 35 µs

ILMT(DLY)

IS to GATE propagation delay V

pulsed from 0 to 1 V 100 ns

PWM COMPARATOR AND SLOPE COMPENSATION

MAX

Maximum duty cycle 90.4% 93% 94.7%

IS to COMP level shift voltage No slope compensation added 1.17 1.5 1.8 V

Slope compensation

D = D

MAX

(with max slope

compensation)

200 mV

IS level shift bias current No slope compensation added 25 µA

剩余45页未读，继续阅读

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