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TPS6293x 电感-输出电容
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TPS6293x 电感-输出电容
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TPS6293x 3.8-V to 30-V, 3-A/2-A Synchronous Buck Converter in a SOT583 Package
1 Features
• Configured for a wide range of applications
– Input voltage range: 3.8 V to 30 V
– Output voltage range: 0.8 V to 22 V
– Ultra-low quiescent current: 12 μA (typical)
– Integrated 76-mΩ and 32-mΩ MOSFETs
– 0.8V ± 1% reference voltage
– Maximum 98% duty cycle operation
– Precision EN threshold
– 3-A (TPS62933) and 2-A (TPS62932)
continuous output current
– Operating junction temperature: –40°C to
150°C
• Ease of use and small solution size
– Peak current control mode with internal
compensation
– Pulse frequency modulation (PFM) for high
light-load efficiency
– Adjustable soft-start time
– 200-kHz to 2.2-MHz selectable frequency
– EMI friendly with frequency spread spectrum
– Support start-up with pre-biased output
– Cycle-by-cycle OC limit for both high-side and
low-side MOSFETs
– Non-latched protections for OTP, OCP, OVP,
UVP, and UVLO
– 1.6-mm × 2.1-mm SOT583
• Create a custom design with the TPS62933 using
the WEBENCH
®
Power Designer
• Create a custom design with the TPS62932 using
the WEBENCH
®
Power Designer
2 Applications
• Building automation, appliances, industrial PC
• Multifunction printers, enterprise projectors
• Portable electronics, connected peripherals
• Smart speakers, monitors
• Distributed power systems with 5-V, 12-V, 19-V,
24-V input
3 Description
The TPS62933/TPS62932 is a high-efficiency, easy-
to-use synchronous buck converter with a wide input
voltage range of 3.8 V to 30 V, and supports up to
3-A/2-A continuous output current and 0.8-V to 22-V
output voltage.
The device employs fixed-frequency peak current
control mode for fast transient response and good
line and load regulation. The optimized internal
loop compensation eliminates external compensation
components. Pulse frequency modulation (PFM)
mode maximizes the light load efficiency. The ULQ
(ultra-low quiescent) feature is extremely beneficial
for long battery lifetime in low-power operation. The
switching frequency can be set by the configuration
of the RT pin in the range of 200 kHz to 2.2 MHz,
which allows the user to optimize system efficiency,
solution size, and bandwidth. The soft-start time can
be adjusted by the external capacitor at the SS pin,
which can minimize the inrush current when driving
large capacitive load. This device also has frequency
spread spectrum feature, which helps with lowering
down EMI noise.
This device is in a small SOT583 (1.6-mm × 2.1-mm)
package with 0.5-mm pin pitch, and has an optimized
pinout for easy PCB layout and promotes good EMI
performance.
Device Information
PART NUMBER PACKAGE
(1)
BODY SIZE (NOM)
TPS62933
SOT583 (8) 1.60 mm × 2.10 mm
TPS62932
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
L
C
BST
C
OUT
R
FBT
R
FBB
VIN
GND
EN
SS
BST
SW
FB
RT
C
IN
V
IN
V
OUT
V
EN
Simplified Schematic
I-Load (A)
Efficiency (%)
0.001 0.005 0.02 0.05 0.1 0.2 0.5 1 2 3
0
20
40
60
80
100
VOUT=3.3V
VOUT=5V
VOUT=12V
TPS62933 Efficiency, V
IN
= 24 V, f
SW
= 500 kHz
TPS62933, TPS62932
SLUSEA4B – JUNE 2021 – REVISED FEBRUARY 2022
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................ 7
8 Detailed Description......................................................13
8.1 Overview................................................................... 13
8.2 Functional Block Diagram......................................... 14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................23
9 Application and Implementation.................................. 25
9.1 Application Information............................................. 25
9.2 Typical Application.................................................... 25
9.3 What to Do and What Not to Do............................... 35
10 Power Supply Recommendations..............................36
11 Layout........................................................................... 37
11.1 Layout Guidelines .................................................. 37
11.2 Layout Example...................................................... 38
12 Device and Documentation Support..........................39
12.1 Device Support....................................................... 39
12.2 Receiving Notification of Documentation Updates..39
12.3 Support Resources................................................. 39
12.4 Trademarks.............................................................39
12.5 Electrostatic Discharge Caution..............................39
12.6 Glossary..................................................................39
13 Mechanical, Packaging, and Orderable
Information.................................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2021) to Revision B (February 2022) Page
• Added the TPS62932......................................................................................................................................... 1
Changes from Revision * (June 2021) to Revision A (December 2021) Page
• Changed document status from Advance Information to Production Data.........................................................1
TPS62933, TPS62932
SLUSEA4B – JUNE 2021 – REVISED FEBRUARY 2022
www.ti.com
2 Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TPS62933 TPS62932
5 Device Comparison Table
PART NUMBER
OUTPUT CURRENT
PFM or FCCM or OOA SS or PG PIN STATUS
TPS62933
3 A
PFM SS Released
TPS62932
2 A
PFM SS Released
TPS62933F 3 A FCCM SS To be released
TPS62933O 3 A OOA PG To be released
TPS62933P 3 A PFM PG To be released
6 Pin Configuration and Functions
SS
1
2
3
4 5
6
7
8
VIN
SW
GND
FB
RT
EN
BST
Figure 6-1. 8-Pin SOT583 DRL Package (Top View)
Table 6-1. Pin Functions
PIN
TYPE
(1)
DESCRIPTION
NAME NO.
RT 1 A
Frequency programming input. Float for 500 kHz, tie to GND for 1.2 MHz, or connect to an
RT timing resistor. See Section 8.3.5 for details.
EN 2 A
Enable input to the converter. Driving EN high or leaving this pin floating enables the
converter. An external resistor divider can be used to implement an adjustable V
IN
UVLO
function.
VIN 3 P
Supply input terminal to internal LDO and high-side FET. Input bypass capacitors must be
directly connected to this pin and GND.
GND 4 G
Ground terminal. Connected to the source of the low-side FET as well as the ground
terminal for the controller circuit. Connect to system ground and the ground side of C
IN
and C
OUT
. The path to C
IN
must be as short as possible.
SW 5 P
Switching output of the convertor. Internally connected to the source of the high-side FET
and drain of the low-side FET. Connect to the power inductor.
BST 6 P
Bootstrap capacitor connection for high-side FET driver. Connect a high-quality, 100-nF
ceramic capacitor from this pin to the SW pin.
SS 7 A
Soft-start and tracking input. An external capacitor connected to this pin sets the internal
voltage reference rising time. See Section 8.3.7 for details. A minimum 6.8-nF ceramic
capacitor must be connected at this pin, which sets the minimum soft-start time to
approximately 1 ms. Do not float.
FB 8 A
Output feedback input. Connect FB to the tap of an external resistor divider from the output
to GND to set output voltage.
(1) A = Analog, P = Power, G = Ground
www.ti.com
TPS62933, TPS62932
SLUSEA4B – JUNE 2021 – REVISED FEBRUARY 2022
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TPS62933 TPS62932
7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to +150°C , unless otherwise noted
(1)
MIN MAX UNIT
Input voltage
V
IN
–0.3 32
V
EN –0.3 6
FB –0.3 6
Output voltage
SW, DC –0.3 32
SW, transient < 10 ns –3 33
BST –0.3 SW + 6
BST–SW –0.3 6
SS –0.3 6
RT –0.3 6
T
J
Operating junction temperature
(2)
–40 150
°C
T
stg
Storage temperature –65 150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Operating at junction temperatures greater than 150°C, although possible, degrades the lifetime of the device.
7.2 ESD Ratings
VALUE UNIT
V
(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins
(1)
±2000
V
Charged device model (CDM), per ANSI/ESDA/JEDEC
JS-002, all pins
(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted
(1)
MIN NOM MAX UNIT
Input voltage
V
IN
3.8 30
V
EN –0.1 5.5
FB –0.1 5.5
Output
voltage
V
OUT
0.8 22
SW, DC –0.1 30
SW, transient < 10 ns –3 32
BST –0.1 SW + 5.5
BST-SW –0.1 5.5
Ouput current I
OUT
TPS62933 0 3
A
TPS62932 0 2
Temperature Operating junction temperature, T
J
–40 150 °C
(1) The Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee
specific performance limits. For compliant specifications, see the Electrical Characteristics.
TPS62933, TPS62932
SLUSEA4B – JUNE 2021 – REVISED FEBRUARY 2022
www.ti.com
4 Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TPS62933 TPS62932
7.4 Thermal Information
THERMAL METRIC
(1)
TPS62933, TPS62932
UNITDRL (SOT583), 8 PINS
JEDEC
(2)
EVM
(3)
R
θJA
Junction-to-ambient thermal resistance 112.2 N/A °C/W
R
θJC(top)
Junction-to-case (top) thermal resistance 29.1 N/A °C/W
R
θJB
Junction-to-board thermal resistance 19.3 N/A °C/W
Ψ
JT
Junction-to-top characterization parameter 1.6 N/A °C/W
Ψ
JB
Junction-to-board characterization parameter 19.2 N/A °C/W
R
θJA_EVM
Junction-to-ambient thermal resistance on official
EVM board
N/A 60.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The value of R
θJA
given in this table is only valid for comparison with other packages and can not be used for design purposes. These
values were simulated on a standard JEDEC board. They do not represent the performance obtained in an actual application.
(3) The real R
θJA
is tested on TI EVM (2 layer, 2-ounce copper thickness).
7.5 Electrical Characteristics
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life
of the product containing it. T
J
= –40°C to +150°C, V
IN
= 3.8 V to 30 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY (VIN PIN)
V
IN
Operation input voltage 3.8 30 V
I
Q
Nonswitching quiescent current EN = 5 V, V
FB
= 0.85 V 12 µA
I
SHDN
Shutdown supply current V
EN
= 0 V 2 µA
V
IN_UVLO
Input undervoltage lockout
thresholds
Rising threshold 3.4 3.6 3.8 V
Falling threshold 3.1 3.3 3.5 V
Hysteresis 300 mV
ENABLE (EN PIN)
V
EN_RISE
Enable threshold Rising enable threshold 1.21 1.28 V
V
EN_FALL
Disable threshold Falling disable threshold 1.1 1.17 V
I
p
EN pullup current V
EN
= 1.0 V 0.7 µA
I
h
EN pullup hysteresis current V
EN
= 1.5 V 1.4 µA
VOLTAGE REFERENCE (FB PIN)
V
FB
FB voltage
T
J
= 25°C 792 800 808 mV
T
J
= 0°C to 85°C 788 800 812 mV
T
J
= –40°C to 150°C 784 800 816 mV
I
FB
Input leakage current V
FB
= 0.8 V 0.15 μA
INTEGRATED POWER MOSFETS
R
DSON_HS
High-side MOSFET on-resistance T
J
= 25°C, V
BST
– SW = 5 V 76 mΩ
R
DSON_LS
Low-side MOSFET on-resistance T
J
= 25°C 32 mΩ
CURRENT LIMIT
I
HS_LIMIT
High-side MOSFET current limit
TPS62933 4.2 5 5.8
A
TPS62932 2.8 3.4 4
I
LS_LIMIT
Low-side MOSFET current limit
TPS62933 2.9 3.8 4.5
A
TPS62932 2 2.5 3
www.ti.com
TPS62933, TPS62932
SLUSEA4B – JUNE 2021 – REVISED FEBRUARY 2022
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TPS62933 TPS62932
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