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BOOT

HDRV

LDRV/OC

COMP

PGOOD

EN/SS

TPS40345

1 10BPVDD

PAD

OUT

GND

Product

Folder

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Now

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Documents

Tools &

Software

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLUSD62

TPS40345

ZHCSH69 –DECEMBER 2017

TPS40345 3V 至至 20V 输输入入同同步步降降压压控控制制器器

1 特特性性

• 输入电压范围：3V 至 20V

• 600kHz 开关频率

• 高侧和低侧 FET R

DS(on)

电流检测

• 可编程热补偿 OCP 电平

• 可编程软启动

• 600mV、1.3% 基准电压

• 电压前馈补偿

• 支持预偏置输出

• 扩频频谱

• 145°C 的热关断保护限制

• 10 引脚 3mm × 3mm VSON 封装，散热垫具有接

地连接

2 应应用用

• 负载点 (POL) 模块

• 打印机

• 数字电视

• 电信

3 说说明明

TPS40345 是一款同步降压控制器，可在 3V 到 20V

的输入电压下工作，可用于成本优化型应用。此控制

器实现了一种电压模式控制架构，具有输入电压前馈补

偿功能，可对输入电压变化做出即时响应。开关频率设

置为 600kHz。

开关频率中添加了扩频频谱 (FSS) 功能，显著降低了

峰值 EMI 噪声，使其更容易符合 EMI 标准。

TPS40345 可提供各种用户可编程功能，其中包括软

启动、过流保护 (OCP) 电平以及环路补偿。

OCP 电平可以通过从 LDRV 引脚连接到电路接地的单

个外部电阻器进行编程。在初始上电过程

中，TPS40345 可进入校准环节，测量 LDRV 引脚电

压，并设置内部 OCP 电压级。在工作期间，器件可在

通电时通过将已编程 OCP 电压电平与低侧 FET 上的

压降进行比较来确定是否发生过流情况。之

后，TPS40345 会进入关断和重启周期，直到故障消

除为止。

器器件件信信息息

(1)

器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））

TPS40345 VSON (10) 3.00mm × 3.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简简化化应应用用示示意意图图

TPS40345

ZHCSH69 –DECEMBER 2017

www.ti.com.cn

目目录录

1 特特性性.......................................................................... 1

2 应应用用.......................................................................... 1

3 说说明明.......................................................................... 1

4 修修订订历历史史记记录录 ........................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 7

7 Detailed Description.............................................. 9

7.1 Overview ................................................................... 9

7.2 Functional Block Diagram ......................................... 9

7.3 Feature Description................................................... 9

7.4 Device Functional Modes........................................ 12

8 Application and Implementation ........................ 13

8.1 Application Information............................................ 13

8.2 Typical Applications ................................................ 13

9 Power Supply Recommendations...................... 17

10 Layout................................................................... 18

10.1 Layout Guidelines ................................................. 18

10.2 Layout Example .................................................... 19

11 器器件件和和文文档档支支持持 ..................................................... 20

11.1 器件支持................................................................ 20

11.2 文档支持................................................................ 20

11.3 接收文档更新通知 ................................................. 20

11.4 社区资源................................................................ 20

11.5 商标 ....................................................................... 20

11.6 静电放电警告......................................................... 20

11.7 Glossary................................................................ 20

12 机机械械、、封封装装和和可可订订购购信信息息....................................... 20

4 修修订订历历史史记记录录

注：之前版本的页码可能与当前版本有所不同。

日日期期修修订订版版本本说说明明

2017 年 12 月 * 初始发行版

5 4 3 2 1

6 7 8 9 10

FB COMP PGOOD EN/SS VDD

BOOT HDRV SW

LDRV/

Thermal Pad

TPS40345

www.ti.com.cn

ZHCSH69 –DECEMBER 2017

5 Pin Configuration and Functions

DRC Package

10-Pin VSON

Top View

Pin Functions

I/O DESCRIPTION

NAME NO.

BOOT 6 I

Gate drive voltage for the high-side N-channel MOSFET. A 0.1-µF capacitor (typical) must be connected

between this pin and SW. For low input voltage operation, an external Schottky diode from BP to BOOT is

recommended to maximize the gate drive voltage for the high-side.

BP 10 O

Output bypass for the internal regulator. Connect a low ESR bypass ceramic capacitor of 1 µF or greater from

this pin to GND.

COMP 4 O Output of the error amplifier and connection node for loop feedback components.

EN/SS 2 I

Logic level input which starts or stops the controller via an external user command. Letting this pin float turns

the controller on. Pulling this pin low disables the controller. This is also the soft-start programming pin. A

capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an

internal current source of 10 µA. The resulting voltage ramp of this pin is also used as a second non-inverting

input to the error amplifier after a 0.8 V (typical) level shift downwards. Output regulation is controlled by the

internal level shifted voltage ramp until that voltage reaches the internal reference voltage of 600 mV – the

voltage ramp of this pin reaches 1.4 V (typical). Optionally, a 267-kΩ resistor from this pin to BP enables the

FSS feature.

FB 5 I

Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal

reference voltage.

PGOOD 3 O Open-drain power good output.

HDRV 7 O Bootstrapped gate drive output for the high-side N-channel MOSFET.

LDRV/OC 9 O

Gate drive output for the low-side synchronous rectifier N-channel MOSFET. A resistor from this pin to GND

is also used to determine the voltage level for OCP. An internal current source of 10 µA flows through the

resistor during initial calibration and that sets up the voltage trip point used for OCP.

VDD 1 I

Power input to the controller. Bypass VDD to GND with a low ESR ceramic capacitor of at least 1 µF close to

the device.

SW 8 O

Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high-

side FET driver.

GND

Thermal

Pad

—

Ground connection to the controller. This is also the thermal pad used to conduct heat from the device. This

connection serves a twofold purpose. The first is to provide an electrical ground connection for the device.

The second is to provide a low thermal impedance path from the device die to the PCB. This pad should be

tied externally to a ground plane.

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