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Intel Ivy Bridge ULV Processor + Panther Point PCH

VIUS3/S4 M/B Schematics Document

REV:0.1

Compal Confidential

2011-12-28

AMD Seymour XT

Model Name : VIUS3/S4

File Name : LA-8951PR01

Compal Confidential

BOM P/N:43

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

Sherry and Royal

0.1

Cover Page

Custom

1 55Thursday, February 02, 2012

2011/06/24 2012/07/12

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

Sherry and Royal

0.1

Cover Page

Custom

1 55Thursday, February 02, 2012

2011/06/24 2012/07/12

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

Sherry and Royal

0.1

Cover Page

Custom

1 55Thursday, February 02, 2012

2011/06/24 2012/07/12

Compal Electronics, Inc.

http://mycomp.su/x/

1 1

2 2

3 3

4 4

File Name :VIUS3/VIUS4

Compal confidential

SPI ROM

BIOS

Std HDMI

USB PORT 3.0 x1 (Left)

25mm*25mm

SATA3.0 HDD CONN

DDR3-1600(1.5V) for Ivy Bridge

6*PCI-E x1

PCI Express (Half)

Mini card Slot 1

FDI *8

100MHz

2.7GT/s

Intel

6*SATA

Single Digital MIC

PCI-E X16

LED BOARD

BlueTooth CONN

MOS Camera

RealTek

ALC259-VC2

Audio Codec

2Channel Speaker

LPC BUS

HD Audio

Int.KBD

ENE KB9012

Touch Pad

DDR3-1066/1333(1.5V) for Sandy Bridge

ual Channel

14*USB2.0

LVDS

Connector

IVY Bridge SV/ULV

(Sandy Bridge)

BGA1023

DMI2 *4

FCBGA 989 Balls

Intel

Panther Point

Connector

gDDR3*4

AMD Seymour XT

VRAM 128MB*16

Audio Combo Jack

(APPLE type)

HeadPhone Output

Microphone Input

PX 5.0

(port0,1 Support SATA3)

SATA3.0 HDD (SSD)

LAN(10/100/Giga)

RJ45 CONN

EMC1403

WLAN/WiMAX

Thermal Sensor

WLAN/WiMAX

PCI-E(WLAN)

USB(WiMAX)

PCI Express (Full)

Mini card Slot 2

mSATA(SSD)

SSD

100MHz

5GT/s

Gen 2

HDMI 1.4a

Processor

Sub-borad

O Board

Chief River

IO Board

4*USB3.0

WLAN/WiMAX

USB PORT 2.0 x2 (Right)

Card Reader RTS 5178 (2in1)

Realtek

8105E-VD (10/100)

8111F-VL (Giga)

POWER BOARD

4MB*1

2MB*1

23mm *23mm

UP TO 1G

Gen 2

IO Board

BANK 0, 1

DDR3-SO-DIMM X1

HM77/HM70

WWAN

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.2

MB Block Diagram

Custom

2 55Thursday, February 02, 2012

2011/07/21 2012/12/31

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.2

MB Block Diagram

Custom

2 55Thursday, February 02, 2012

2011/07/21 2012/12/31

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.2

MB Block Diagram

Custom

2 55Thursday, February 02, 2012

2011/07/21 2012/12/31

Compal Electronics, Inc.

http://mycomp.su/x/

1 1

2 2

3 3

4 4

USB 2.0 Port

3 External

USB Port

USB 3.0 Port (Left Side)

Camera (LVDS)

UHCI0

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

EHCI1

EHCI2

USB Port Table

Board ID / SKU ID Table for AD channelBOARD ID Table

EC SM Bus1 address

Device

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Vcc 3.3V +/- 5%

100K +/- 5%Ra/Rc/Re

Board ID

Rb / Rd / Rf V min

8.2K +/- 5%

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

0.503 V

0.819 V

0.538 V

0.875 V

AD_BID

V typ

AD_BID

max

18K +/- 5%

33K +/- 5%

56K +/- 5%

100K +/- 5%

200K +/- 5%

3.300 V

0 V 0 V

7 NC

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

2.341 V

1.185 V 1.264 V

Board ID

PCB Revision

0.1

PCH SM Bus address

Device Address

Address

Voltage Rails

Unpop

BTO Item BOM Structure

ON ON

OFF

LOW

LOW LOW LOW LOW

LOWLOWLOW

LOW

HIGH HIGH HIGH HIGH

HIGHHIGHHIGH

HIGH

EC SM Bus2 address

Device

Smart Battery

0001 011X b

Blue Tooth BT@

Connector ME@

USB/B (Right Side USB-BD)

Mini Card(WLAN)

+3VALW

+3VS

PCH

Thermal

Sensor

SML0CLK

SML0DATA

PCH

SMB_EC_CK2

SOURCE

KB9012

VGA BATT KB9012 SODIMM

SMBUS Control Table

SMBCLK

SMBDATA

PCH

WLAN

WWAN

SMB_EC_DA2

SMB_EC_CK1

SMB_EC_DA1

X V

KB9012

SML1CLK

SML1DATA

PCH

XX X

USB Port (Right Side CR-BD)

+3VS

Interna-Intel-USB3.0 IU3@

+3VS

+3VALW

+5VS

+CPU_CORE

X X

+1.05VS_VTT

power

plane

S5 S4/ Battery only

X X X

State

+1.5VS

+1.5V

S5 S4/AC & Battery

on't exist

S5 S4/AC

+5VALW

+VCC_GFXCORE_AXG

+1.8VS

+0.75VS

+VGA_CORE

HDMI HDMI@

BOM Structure Table

EVT

DVT

PVT

45 LEVEL 45@

10/100 LAN 8105E@

GIGA LAN 8111F@

Thermal Sensor F75303M

1001_101xb

PX@ GPU:Seymour XT

EVT

DVT

PVT

Porject Phase

G-series

Y-series

AMD-GPU SM Bus address

Device Address

Internal thermal sensor

1001 111Xb (0x9E)

X (USB PORT disabled on HM70 )

Interna-Intel-USB2.0 IU2@

HDD2 (HM70 SATA 2.0) HDD2@

HDD1 (HM77 SATA 3.0) HDD1@

INTEL UMA only UMA@

USB 3.0

xHCI1

xHCI2

xHCI3

xHCI4

HM70 Disable xHCI3,xHCI4

HM70 Disable P1,P3

HM77

SATA Port Table

SATA P0

SSD

SATA P1

SATA P2

SATA P3

SATA P5

SATA P4

HM70

GEN3/2/1

DisableGEN3/2/1

GEN3/2/1

GEN2/1

Disable

HDD (HM77)

HDD (HM70)

HM77

PCIe Port Table

LAN

PCIe P1

PCIe P2

PCIe P3

PCIe P5

PCIe P4

HM70

Enable

HM70 Disable P5,P6,P7,P8

PCIe P6

PCIe P7

PCIe P8

Enable

Disable

Enable

Disable

WLAN

USB/B (Right Side USB-BD)

PX5@

+1.5V_IO

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-7981P

0.2

Notes List

3 55Friday, February 03, 2012

2011/06/15 2012/07/11

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-7981P

0.2

Notes List

3 55Friday, February 03, 2012

2011/06/15 2012/07/11

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-7981P

0.2

Notes List

3 55Friday, February 03, 2012

2011/06/15 2012/07/11

Compal Electronics, Inc.

http://mycomp.su/x/

D D

C C

B B

A A

Note: Do not drive any IOs before VDDR3 is ramped up.

VDDR3(3.3VGS)

VDD_CT(1.8V)

VDDC/VDDCI(1.12V)

PERSTb

REFCLK

Straps Valid

Straps Reset

Power-Up/Down Sequence

VDDR1(1.5VGS)

1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up

sequence, though a shorter ramp-up duration is preferred.

2. VDDR3 should ramp-up before or simultaneously with VDDC.

3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before

DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.

4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and

VDD_CT have ramped up.

5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to

ramp-up (or vice versa).)

PCIE_VDDC(1.0V)

Global ASIC Reset

T4+16clock

dGPU Power Pins Max current

190mA

575mA

1679mAPCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT,

DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,

DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,

DPLL_PVDD, MPV18, and SPV18

12.9A

2.8A

70mA

VDDR1

BIF_VDDC (current consumption = 55mA@1.0V, in

BACO mode)

BIF_VDDC=VGA_CORE When GPU enable

BIF_VDDC=1.0V When BACO

VDDR3 , and A2VDD

PCIE_VDDC

DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and

SPV10

Voltage

VDDC/VDDCI

VDDC

3.3V

1.0V

1.8V

1.12V

1.5V

Same as

OFF

PX 3.0

OFF

MOS

OFF

BACO Mode

OFF

Same as

OFF

PCIE_VDDC

+1.0VGS

+VGA_CORE

+1.5VGS

+3.3VGS

+1.8VGS

iGPU

+1.5V

PXS_PWREN

+3.3VALW

dGPU

+1.0V

PXS_RST#

+1.8V

BACO Switch

PE_EN

BIF_VDDC

PWRGOOD

PX_mode

Without BACO option :

PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON

PXS_RST# : Low -> Reset dGPU ; High ->Normal operation

PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)

PXS_RST# : High ->Normal operation (dGPU is not reset on BACO mode)

BACO option :

SI4800

Regulator

PCB partCPU part

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-7981P

0.2

VGA Notes List

Custom

4 55Thursday, February 02, 2012

2011/06/15 2012/07/11

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-7981P

0.2

VGA Notes List

Custom

4 55Thursday, February 02, 2012

2011/06/15 2012/07/11

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-7981P

0.2

VGA Notes List

Custom

4 55Thursday, February 02, 2012

2011/06/15 2012/07/11

Compal Electronics, Inc.

UCPU1

I5_3427 1.8G

CPU2@

SA00005L900

UCPU1

I5_3427 1.8G

CPU2@

SA00005L900

UCPU1

977_1.4G

CPU4@

SA00005BJ40

UCPU1

977_1.4G

CPU4@

SA00005BJ40

ZZZ1

Hynix

H512@

X7641338L02

ZZZ1

Hynix

H512@

X7641338L02

UCPU1

I3_3217 1.8G

CPU1@

SA00005L510

UCPU1

I3_3217 1.8G

CPU1@

SA00005L510

ZZZ2

Hynix

S512@

X7641338L01

ZZZ2

Hynix

S512@

X7641338L01

ZZZ5

PCB 0R LA-8951P REV0 M/B

DA60000TO00

ZZZ5

PCB 0R LA-8951P REV0 M/B

DA60000TO00

ZZZ3

Hynix

S1G@

X7641338L03

ZZZ3

Hynix

S1G@

X7641338L03

UCPU1

I5_2557 1.4G

CPU3@

SA00004VZ00

UCPU1

I5_2557 1.4G

CPU3@

SA00004VZ00

ZZZ4

Hynix

H1G@

X7641338L04

ZZZ4

Hynix

H1G@

X7641338L04

http://mycomp.su/x/

1 1

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PEG_ICOMPI and RCOMPO signals should be

shorted and routed

with - max length = 500 mils - typical

impedance = 43 mohms

PEG_ICOMPO signals should be routed with -

max length = 500 mils

- typical impedance = 14.5 mohms

Typ- suggest 220nF. The change in AC capacitor

value from 100nF to 220nF is to enable

compatibility with future platforms having PCIE

Gen3 (8GT/s)

eDP_COMPIO and ICOMPO signals

should be shorted near balls and

routed with typical impedance

<25 mohms

can't be left floating

,even if disable eDP function...

W=12mil L=500mil S=15mil

Layout placement: Place close to U8 (GPU)

EDP_COMP

PEG_COMP

PEG_GTX_C_HRX_N15

PEG_GTX_C_HRX_N14

PEG_GTX_C_HRX_N13

PEG_GTX_C_HRX_N12

PEG_GTX_C_HRX_N11

PEG_GTX_C_HRX_N10

PEG_GTX_C_HRX_N9

PEG_GTX_C_HRX_N8

PEG_GTX_C_HRX_N7

PEG_GTX_C_HRX_N6

PEG_GTX_C_HRX_N5

PEG_GTX_C_HRX_N4

PEG_GTX_C_HRX_N3

PEG_GTX_C_HRX_N2

PEG_GTX_C_HRX_N1

PEG_GTX_C_HRX_N0

PEG_GTX_C_HRX_P15

PEG_GTX_C_HRX_P14

PEG_GTX_C_HRX_P13

PEG_GTX_C_HRX_P12

PEG_GTX_C_HRX_P11

PEG_GTX_C_HRX_P10

PEG_GTX_C_HRX_P9

PEG_GTX_C_HRX_P8

PEG_GTX_C_HRX_P7

PEG_GTX_C_HRX_P6

PEG_GTX_C_HRX_P5

PEG_GTX_C_HRX_P4

PEG_GTX_C_HRX_P3

PEG_GTX_C_HRX_P2

PEG_GTX_C_HRX_P1

PEG_GTX_C_HRX_P0

PEG_HTX_GRX_N15

PEG_HTX_GRX_N14

PEG_HTX_GRX_N13

PEG_HTX_GRX_N12

PEG_HTX_GRX_N11

PEG_HTX_GRX_N10

PEG_HTX_GRX_N9

PEG_HTX_GRX_N8

PEG_HTX_GRX_N7

PEG_HTX_GRX_N6

PEG_HTX_GRX_N5

PEG_HTX_GRX_N4

PEG_HTX_GRX_N3

PEG_HTX_GRX_N2

PEG_HTX_GRX_N1

PEG_HTX_GRX_N0

PEG_HTX_GRX_P15

PEG_HTX_GRX_P14

PEG_HTX_GRX_P13

PEG_HTX_GRX_P12

PEG_HTX_GRX_P11

PEG_HTX_GRX_P10

PEG_HTX_GRX_P9

PEG_HTX_GRX_P8

PEG_HTX_GRX_P7

PEG_HTX_GRX_P6

PEG_HTX_GRX_P5

PEG_HTX_GRX_P4

PEG_HTX_GRX_P3

PEG_HTX_GRX_P2

PEG_HTX_GRX_P1

PEG_HTX_GRX_P0

PEG_GTX_HRX_N0

PEG_GTX_HRX_N4

PEG_GTX_HRX_N2

PEG_GTX_HRX_N3

PEG_GTX_HRX_N1

PEG_GTX_HRX_N5

PEG_GTX_HRX_N6

PEG_GTX_HRX_N7

PEG_GTX_HRX_N8

PEG_GTX_HRX_N9

PEG_GTX_HRX_N10

PEG_GTX_HRX_N11

PEG_GTX_HRX_N12

PEG_GTX_HRX_N13

PEG_GTX_HRX_N14

PEG_GTX_HRX_N15

PEG_GTX_HRX_P0

PEG_GTX_HRX_P1

PEG_GTX_HRX_P2

PEG_GTX_HRX_P3

PEG_GTX_HRX_P4

PEG_GTX_HRX_P5

PEG_GTX_HRX_P6

PEG_GTX_HRX_P7

PEG_GTX_HRX_P8

PEG_GTX_HRX_P9

PEG_GTX_HRX_P10

PEG_GTX_HRX_P11

PEG_GTX_HRX_P12

PEG_GTX_HRX_P13

PEG_GTX_HRX_P14

PEG_GTX_HRX_P15

PEG_HTX_C_GRX_N0

PEG_HTX_C_GRX_N1

PEG_HTX_C_GRX_N2

PEG_HTX_C_GRX_N3

PEG_HTX_C_GRX_N4

PEG_HTX_C_GRX_N5

PEG_HTX_C_GRX_N6

PEG_HTX_C_GRX_N7

PEG_HTX_C_GRX_N8

PEG_HTX_C_GRX_N9

PEG_HTX_C_GRX_N10

PEG_HTX_C_GRX_N11

PEG_HTX_C_GRX_N12

PEG_HTX_C_GRX_N13

PEG_HTX_C_GRX_N14

PEG_HTX_C_GRX_N15

PEG_HTX_C_GRX_P0

PEG_HTX_C_GRX_P1

PEG_HTX_C_GRX_P2

PEG_HTX_C_GRX_P3

PEG_HTX_C_GRX_P4

PEG_HTX_C_GRX_P5

PEG_HTX_C_GRX_P6

PEG_HTX_C_GRX_P7

PEG_HTX_C_GRX_P8

PEG_HTX_C_GRX_P9

PEG_HTX_C_GRX_P10

PEG_HTX_C_GRX_P11

PEG_HTX_C_GRX_P12

PEG_HTX_C_GRX_P13

PEG_HTX_C_GRX_P14

PEG_HTX_C_GRX_P15

DMI_CTX_PRX_P0[15]

DMI_CRX_PTX_P0[15]

DMI_CTX_PRX_N1[15]

DMI_CRX_PTX_N1[15]

DMI_CTX_PRX_P3[15]

DMI_CRX_PTX_P3[15]

DMI_CTX_PRX_P2[15]

DMI_CTX_PRX_N0[15]

DMI_CRX_PTX_N3[15]

DMI_CRX_PTX_P2[15]

DMI_CTX_PRX_N3[15]

DMI_CTX_PRX_P1[15]

DMI_CRX_PTX_N0[15]

DMI_CRX_PTX_N2[15]

DMI_CRX_PTX_P1[15]

DMI_CTX_PRX_N2[15]

FDI_CTX_PRX_N0[15]

FDI_CTX_PRX_N1[15]

FDI_CTX_PRX_N2[15]

FDI_CTX_PRX_N3[15]

FDI_CTX_PRX_N4[15]

FDI_CTX_PRX_N5[15]

FDI_CTX_PRX_N6[15]

FDI_CTX_PRX_N7[15]

FDI_CTX_PRX_P0[15]

FDI_CTX_PRX_P1[15]

FDI_CTX_PRX_P2[15]

FDI_CTX_PRX_P3[15]

FDI_CTX_PRX_P4[15]

FDI_CTX_PRX_P5[15]

FDI_CTX_PRX_P6[15]

FDI_CTX_PRX_P7[15]

FDI_FSYNC0[15]

FDI_FSYNC1[15]

FDI_INT[15]

FDI_LSYNC0[15]

FDI_LSYNC1[15]

PEG_GTX_HRX_N[0..15] [22]

PEG_HTX_C_GRX_P[0..15] [22]

PEG_HTX_C_GRX_N[0..15] [22]

PEG_GTX_HRX_P[0..15] [22]

+1.05VS_VTT

Title

Size Document Number Rev

Date: Sheet

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

Sherry and Royal

0.1

PROCESSOR(1/7) DMI,FDI,PEG

Custom

5 55Thursday, February 02, 2012

2011/06/24 2012/07/12

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

Sherry and Royal

0.1

PROCESSOR(1/7) DMI,FDI,PEG

Custom

5 55Thursday, February 02, 2012

2011/06/24 2012/07/12

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

Sherry and Royal

0.1

PROCESSOR(1/7) DMI,FDI,PEG

Custom

5 55Thursday, February 02, 2012

2011/06/24 2012/07/12

Compal Electronics, Inc.

C593 0.22U_0402_6.3V6KPX@C593 0.22U_0402_6.3V6KPX@

1 2

C584 0.22U_0402_6.3V6KPX@C584 0.22U_0402_6.3V6KPX@

1 2

C573 0.22U_0402_6.3V6KPX@C573 0.22U_0402_6.3V6KPX@

1 2

C263 0.22U_0402_6.3V6KPX@C263 0.22U_0402_6.3V6KPX@

1 2

C264 0.22U_0402_6.3V6KPX@C264 0.22U_0402_6.3V6KPX@

1 2

C571 0.22U_0402_6.3V6KPX@C571 0.22U_0402_6.3V6KPX@

1 2

C265 0.22U_0402_6.3V6KPX@C265 0.22U_0402_6.3V6KPX@

1 2

C574 0.22U_0402_6.3V6KPX@C574 0.22U_0402_6.3V6KPX@

1 2

R247

24.9_0402_1%

R247

24.9_0402_1%

C582 0.22U_0402_6.3V6KPX@C582 0.22U_0402_6.3V6KPX@

1 2

C247 0.22U_0402_6.3V6KPX@C247 0.22U_0402_6.3V6KPX@

1 2

C246 0.22U_0402_6.3V6KPX@C246 0.22U_0402_6.3V6KPX@

1 2

C567 0.22U_0402_6.3V6KPX@C567 0.22U_0402_6.3V6KPX@

1 2

C256 0.22U_0402_6.3V6KPX@C256 0.22U_0402_6.3V6KPX@

1 2

C587 0.22U_0402_6.3V6KPX@C587 0.22U_0402_6.3V6KPX@

1 2

PCI EXPRESS -- GRAPHICS

DMI Intel(R) FDI

eDP

UCPU1A

IVY-BRIDGE_BGA1023

PCI EXPRESS -- GRAPHICS

DMI Intel(R) FDI

eDP

UCPU1A

IVY-BRIDGE_BGA1023

DMI_RX#[0]

DMI_RX#[1]

DMI_RX#[2]

DMI_RX#[3]

P10

DMI_RX[0]

DMI_RX[1]

DMI_RX[2]

DMI_RX[3]

P11

DMI_TX#[0]

DMI_TX#[1]

DMI_TX#[2]

DMI_TX#[3]

DMI_TX[0]

DMI_TX[1]

DMI_TX[3]

DMI_TX[2]

FDI0_TX#[0]

FDI0_TX#[1]

W11

FDI0_TX#[2]

FDI0_TX#[3]

AA6

FDI1_TX#[0]

FDI1_TX#[1]

FDI1_TX#[2]

FDI1_TX#[3]

AC9

FDI0_TX[0]

FDI0_TX[1]

W10

FDI0_TX[2]

FDI0_TX[3]

AA7

FDI1_TX[0]

FDI1_TX[1]

FDI1_TX[2]

AA3

FDI1_TX[3]

AC8

FDI0_FSYNC

AA11

FDI1_FSYNC

AC12

FDI_INT

U11

FDI0_LSYNC

AA10

FDI1_LSYNC

AG8

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]

H22

PEG_RX#[1]

J21

PEG_RX#[2]

B22

PEG_RX#[3]

D21

PEG_RX#[4]

A19

PEG_RX#[5]

D17

PEG_RX#[6]

B14

PEG_RX#[7]

D13

PEG_RX#[8]

A11

PEG_RX#[9]

B10

PEG_RX#[10]

PEG_RX#[11]

PEG_RX#[12]

PEG_RX#[13]

PEG_RX#[14]

PEG_RX#[15]

PEG_RX[0]

K22

PEG_RX[1]

K19

PEG_RX[2]

C21

PEG_RX[3]

D19

PEG_RX[4]

C19

PEG_RX[5]

D16

PEG_RX[6]

C13

PEG_RX[7]

D12

PEG_RX[8]

C11

PEG_RX[9]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

G22

PEG_TX#[1]

C23

PEG_TX#[2]

D23

PEG_TX#[3]

F21

PEG_TX#[4]

H19

PEG_TX#[5]

C17

PEG_TX#[6]

K15

PEG_TX#[7]

F17

PEG_TX#[8]

F14

PEG_TX#[9]

A15

PEG_TX#[10]

J14

PEG_TX#[11]

H13

PEG_TX#[12]

M10

PEG_TX#[13]

F10

PEG_TX#[14]

PEG_TX#[15]

PEG_TX[0]

F22

PEG_TX[1]

A23

PEG_TX[2]

D24

PEG_TX[3]

E21

PEG_TX[4]

G19

PEG_TX[5]

B18

PEG_TX[6]

K17

PEG_TX[7]

G17

PEG_TX[8]

E14

PEG_TX[9]

C15

PEG_TX[10]

K13

PEG_TX[11]

G13

PEG_TX[12]

K10

PEG_TX[13]

G10

PEG_TX[14]

PEG_TX[15]

eDP_AUX

AF4

eDP_AUX#

AG4

eDP_TX[0]

AC1

eDP_TX[1]

AA4

eDP_TX[2]

AE10

eDP_TX[3]

AE6

eDP_COMPIO

AF3

eDP_HPD#

AG11

eDP_ICOMPO

AD2

eDP_TX#[0]

AC3

eDP_TX#[1]

AC4

eDP_TX#[2]

AE11

eDP_TX#[3]

AE7

C262 0.22U_0402_6.3V6KPX@C262 0.22U_0402_6.3V6KPX@

1 2

C585 0.22U_0402_6.3V6KPX@C585 0.22U_0402_6.3V6KPX@

1 2

C253 0.22U_0402_6.3V6KPX@C253 0.22U_0402_6.3V6KPX@

1 2

C568 0.22U_0402_6.3V6KPX@C568 0.22U_0402_6.3V6KPX@

1 2

R249

24.9_0402_1%

R249

24.9_0402_1%

C250 0.22U_0402_6.3V6KPX@C250 0.22U_0402_6.3V6KPX@

1 2

C595 0.22U_0402_6.3V6KPX@C595 0.22U_0402_6.3V6KPX@

1 2

C249 0.22U_0402_6.3V6KPX@C249 0.22U_0402_6.3V6KPX@

1 2

C564 0.22U_0402_6.3V6KPX@C564 0.22U_0402_6.3V6KPX@

1 2

C272 0.22U_0402_6.3V6KPX@C272 0.22U_0402_6.3V6KPX@

1 2

C575 0.22U_0402_6.3V6KPX@C575 0.22U_0402_6.3V6KPX@

1 2

C245 0.22U_0402_6.3V6KPX@C245 0.22U_0402_6.3V6KPX@

1 2

C576 0.22U_0402_6.3V6KPX@C576 0.22U_0402_6.3V6KPX@

1 2

C259 0.22U_0402_6.3V6KPX@C259 0.22U_0402_6.3V6KPX@

1 2

C590 0.22U_0402_6.3V6KPX@C590 0.22U_0402_6.3V6KPX@

1 2

C258 0.22U_0402_6.3V6KPX@C258 0.22U_0402_6.3V6KPX@

1 2

C267 0.22U_0402_6.3V6KPX@C267 0.22U_0402_6.3V6KPX@

1 2

C566 0.22U_0402_6.3V6KPX@C566 0.22U_0402_6.3V6KPX@

1 2

C274 0.22U_0402_6.3V6KPX@C274 0.22U_0402_6.3V6KPX@

1 2

C592 0.22U_0402_6.3V6KPX@C592 0.22U_0402_6.3V6KPX@

1 2

C255 0.22U_0402_6.3V6KPX@C255 0.22U_0402_6.3V6KPX@

1 2

C276 0.22U_0402_6.3V6KPX@C276 0.22U_0402_6.3V6KPX@

1 2

C562 0.22U_0402_6.3V6KPX@C562 0.22U_0402_6.3V6KPX@

1 2

C254 0.22U_0402_6.3V6KPX@C254 0.22U_0402_6.3V6KPX@

1 2

C586 0.22U_0402_6.3V6KPX@C586 0.22U_0402_6.3V6KPX@

1 2

C271 0.22U_0402_6.3V6KPX@C271 0.22U_0402_6.3V6KPX@

1 2

C257 0.22U_0402_6.3V6KPX@C257 0.22U_0402_6.3V6KPX@

1 2

C561 0.22U_0402_6.3V6KPX@C561 0.22U_0402_6.3V6KPX@

1 2

C594 0.22U_0402_6.3V6KPX@C594 0.22U_0402_6.3V6KPX@

1 2

C589 0.22U_0402_6.3V6KPX@C589 0.22U_0402_6.3V6KPX@

1 2

C252 0.22U_0402_6.3V6KPX@C252 0.22U_0402_6.3V6KPX@

1 2

C569 0.22U_0402_6.3V6KPX@C569 0.22U_0402_6.3V6KPX@

1 2

C269 0.22U_0402_6.3V6KPX@C269 0.22U_0402_6.3V6KPX@

1 2

C244 0.22U_0402_6.3V6KPX@C244 0.22U_0402_6.3V6KPX@

1 2

C563 0.22U_0402_6.3V6KPX@C563 0.22U_0402_6.3V6KPX@

1 2

C266 0.22U_0402_6.3V6KPX@C266 0.22U_0402_6.3V6KPX@

1 2

C591 0.22U_0402_6.3V6KPX@C591 0.22U_0402_6.3V6KPX@

1 2

C572 0.22U_0402_6.3V6KPX@C572 0.22U_0402_6.3V6KPX@

1 2

C268 0.22U_0402_6.3V6KPX@C268 0.22U_0402_6.3V6KPX@

1 2

C583 0.22U_0402_6.3V6KPX@C583 0.22U_0402_6.3V6KPX@

1 2

C248 0.22U_0402_6.3V6KPX@C248 0.22U_0402_6.3V6KPX@

1 2

C251 0.22U_0402_6.3V6KPX@C251 0.22U_0402_6.3V6KPX@

1 2

C596 0.22U_0402_6.3V6KPX@C596 0.22U_0402_6.3V6KPX@

1 2

C273 0.22U_0402_6.3V6KPX@C273 0.22U_0402_6.3V6KPX@

1 2

C570 0.22U_0402_6.3V6KPX@C570 0.22U_0402_6.3V6KPX@

1 2

C597 0.22U_0402_6.3V6KPX@C597 0.22U_0402_6.3V6KPX@

1 2

C565 0.22U_0402_6.3V6KPX@C565 0.22U_0402_6.3V6KPX@

1 2

C275 0.22U_0402_6.3V6KPX@C275 0.22U_0402_6.3V6KPX@

1 2

C270 0.22U_0402_6.3V6KPX@C270 0.22U_0402_6.3V6KPX@

1 2

C588 0.22U_0402_6.3V6KPX@C588 0.22U_0402_6.3V6KPX@

1 2

C277 0.22U_0402_6.3V6KPX@C277 0.22U_0402_6.3V6KPX@

1 2

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