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Single Root I/O Virtualization and

Sharing Specification

Revision 1.1

January 20, 2010

SINGLE ROOT I/O VIRTUALIZATION AND SHARING SPECIFICATION, REV. 1.1

Contents

OBJECTIVE OF THE SPECIFICATION................................................................................. 7

DOCUMENT ORGANIZATION................................................................................................ 7

DOCUMENTATION CONVENTIONS..................................................................................... 7

TERMS AND ABBREVIATIONS.............................................................................................. 8

REFERENCE DOCUMENTS..................................................................................................... 9

1. ARCHITECTURAL OVERVIEW

................................................................................... 11

1.1. PCI TECHNOLOGIES INTEROPERABILITY........................................................................ 23

2. INITIALIZATION AND RESOURCE ALLOCATION ................................................ 25

2.1. SR-IOV RESOURCE DISCOVERY.................................................................................... 25

2.1.1. Configuring SR-IOV Capabilities......................................................................... 25

2.1.2. VF Discovery ........................................................................................................ 26

2.1.3. Function Dependency Lists................................................................................... 29

2.1.4. Interrupt Resource Allocation............................................................................... 29

2.2. RESET MECHANISMS...................................................................................................... 29

2.2.1. Conventional Reset ............................................................................................... 29

2.2.2. FLR That Targets a VF......................................................................................... 30

2.2.3. FLR That Targets a PF......................................................................................... 30

2.3. IOV RE-INITIALIZATION AND REALLOCATION............................................................... 30

2.4. VF MIGRATION.............................................................................................................. 30

2.4.1. Initial VF State...................................................................................................... 31

2.4.2. VF Migration State Transitions............................................................................ 32

3. CONFIGURATION

............................................................................................................ 35

3.1. O

VERVIEW ..................................................................................................................... 35

3.2. C

ONFIGURATION SPACE................................................................................................. 35

3.3. SR-IOV EXTENDED CAPABILITY................................................................................... 35

3.3.1. SR-IOV Extended Capability Header (00h).......................................................... 37

3.3.2. SR-IOV Capabilities (04h)

.................................................................................... 37

3.3.3. SR-IOV Control (08h)........................................................................................... 39

3.3.4. SR-IOV Status (0Ah)

............................................................................................. 42

3.3.5. InitialVFs (0Ch).................................................................................................... 43

3.3.6. TotalVFs (0Eh)...................................................................................................... 43

3.3.7. NumVFs (10h)

....................................................................................................... 44

3.3.8. Function Dependency Link (12h).......................................................................... 44

3.3.9. First VF Offset (14h)

............................................................................................. 46

3.3.10. VF Stride (16h)

..................................................................................................... 46

3.3.11. VF Device ID (1Ah) .............................................................................................. 47

3.3.12. Supported P

age Sizes (1Ch).................................................................................. 47

SINGLE ROOT I/O VIRTUALIZATION AND SHARING SPECIFICATION, REV. 1.1

3.3.13. System Page Size (20h)......................................................................................... 47

3.3.14. VF BAR0, VF BAR1, … VF BAR5 (24h ... 38h).................................................... 48

3.3.15. VF Migration State Array Offset (3Ch) ................................................................ 49

3.4. PF/VF

CONFIGURATION SPACE HEADER ....................................................................... 52

3.4.1. Type 0 Configuration Space Header..................................................................... 53

3.5. PCI

EXPRESS CAPABILITY ............................................................................................. 57

3.5.1. PCI Express Capability List Register (Offset 00h)............................................... 59

3.5.2. PCI Express Capabilities Register (Offset 02h) ................................................... 59

3.5.3. Device Capabilities Register (Offset 04h) ............................................................ 60

3.5.4. Device Control Register (Offset 08h) ................................................................... 61

3.5.5. Device Status Register (Offset 0Ah)...................................................................... 62

3.5.6. Link Capabilities Register (Offset 0Ch)................................................................ 63

3.5.7. Link Control Register (Offset 10h) ....................................................................... 63

3.5.8. Link Status Register (Offset 12h).......................................................................... 65

3.5.9. Device Capabilities 2 Register (Offset 24h) ......................................................... 65

3.5.10. Device Control 2 Register (Offset 28h) ................................................................ 66

3.5.11. Device Status 2 Register (Offset 2Ah)................................................................... 66

3.5.12. Link Capabilities 2 Register (Offset 2Ch)............................................................. 66

3.5.13. Link Control 2 Register (Offset 30h) .................................................................... 66

3.5.14. Link Status 2 Register (Offset 32h)....................................................................... 67

3.6. PCI STANDARD CAPABILITIES ....................................................................................... 67

3.6.1. VPD Capability..................................................................................................... 68

3.7. PCI EXPRESS EXTENDED CAPABILITIES......................................................................... 68

3.7.1. Virtual Channel/MFVC......................................................................................... 69

3.7.2. Access Control Services (ACS) Extended Capability ........................................... 69

3.7.3. Alternative Routing ID Interpretation Extended Capability (ARI)....................... 71

3.7.4. Address Translation Services Extended Capability (ATS).................................... 71

3.7.5. MR-IOV................................................................................................................. 72

3.7.6. Multicast ............................................................................................................... 73

3.7.7. Page Request Interface (PRI) ............................................................................... 73

3.7.8. Dynamic Power Allocation (DPA)

........................................................................ 74

3.7.9. TLP Processing Hint (TPH).................................................................................. 74

4. ERROR H

ANDLING......................................................................................................... 75

4.1. B

ASELINE ERROR REPORTING........................................................................................ 75

4.2. ADVANCED ERROR REPORTING ..................................................................................... 76

4.2.1. VF Header Log ..................................................................................................... 76

4.2.2. Advanced Error Reporting Capability

.................................................................. 77

4.2.3. Advanced Error Reporting Extended Capability Header (Offset 00h)................. 77

4.2.4. Uncorrectable Error Status Register (Offset 04h)................................................ 78

4.2.5. Uncorrectable Error Mask Register (Offset 08h)

................................................. 78

4.2.6. Uncorrectable Error Severity Register (Offset 0Ch)............................................ 79

4.2.7. Correctable Error Status Register (Offset 10h)

.................................................... 80

4.2.8. Correctable Error Mask Register (Offset 14h)..................................................... 80

4.2.9. Advanced Error Capabilities and Control Register (Offset 18h)

......................... 81

4.2.10. Header Log Register (Offset 1Ch)

........................................................................ 81

4.2.11. Root Error Command Register (Offset 2Ch)

........................................................ 82

SINGLE ROOT I/O VIRTUALIZATION AND SHARING SPECIFICATION, REV. 1.1 
 
  5
4.2.12.  Root Error Status Register (Offset 30h)................................................................ 82 
4.2.13.  Correctable Error Source Identification Register (Offset 34h)............................ 82 
4.2.14.  Error Source Identification Register (Offset 36h) ................................................ 82 
4.2.15.  TLP Prefix Log Register (Offset 38h)................................................................... 82 
5.  INTERRUPTS..................................................................................................................... 83 
5.1. INTERRUPT MECHANISMS .............................................................................................. 83 
5.1.1.  MSI Interrupts....................................................................................................... 83 
5.1.2.  MSI-X Interrupts................................................................................................... 84 
5.1.3.  Address Range Isolation....................................................................................... 84 
6.  POWER MANAGEMENT ................................................................................................ 85 
6.1. VF DEVICE POWER MANAGEMENT STATES................................................................... 85 
6.2. PF DEVICE POWER MANAGEMENT STATES ................................................................... 85 
6.3. LINK POWER MANAGEMENT STATE............................................................................... 86 
6.4. VF POWER MANAGEMENT CAPABILITY ........................................................................ 86 
ACKNOWLEDGEMENTS ....................................................................................................... 89 
 
Figures 
FIGURE  1-1:  GENERIC PLATFORM CONFIGURATION...................................................................... 11 
FIGURE  1-2:  GENERIC PLATFORM CONFIGURATION WITH A VI AND MULTIPLE SI........................ 12 
FIGURE  1-3:  GENERIC PLATFORM CONFIGURATION WITH SR-IOV AND IOV ENABLERS.............. 14 
FIGURE  1-4:  EXAMPLE MULTI-FUNCTION DEVICE........................................................................ 16 
FIGURE  1-5:  EXAMPLE SR-IOV SINGLE PF CAPABLE DEVICE...................................................... 17 
FIGURE  1-6:  EXAMPLE SR-IOV MULTI-PF CAPABLE DEVICE ...................................................... 19 
FIGURE  1-7:  EXAMPLE SR-IOV DEVICE WITH MULTIPLE BUS NUMBERS..................................... 21 
FIGURE  1-8:  EXAMPLE SR-IOV DEVICE WITH A MIXTURE OF FUNCTION TYPES .......................... 22 
F
IGURE  1-9:  I/O VIRTUALIZATION INTEROPERABILITY................................................................. 23 
FIGURE  2-1:  BAR SPACE EXAMPLE FOR SINGLE BAR DEVICE..................................................... 26 
F
IGURE  2-2:  INITIAL VF MIGRATION STATE ARRAY..................................................................... 31 
F
IGURE  2-3:  VF MIGRATION STATE DIAGRAM ............................................................................. 32 
FIGURE  3-1:  SINGLE ROOT I/O VIRTUALIZATION EXTENDED CAPABILITIES ................................. 36 
FIGURE  3-2:  TYPE 0 CONFIGURATION SPACE HEADER.................................................................. 53 
F
IGURE  3-3:  PCI EXPRESS CAPABILITY STRUCTURE..................................................................... 58 
FIGURE  3-4:  PCI EXPRESS CAPABILITY LIST REGISTER ................................................................ 59 
F
IGURE  3-5:  PCI EXPRESS CAPABILITIES REGISTER...................................................................... 59 
FIGURE  3-6:  DEVICE CAPABILITIES REGISTER .............................................................................. 60 
FIGURE  3-7:  DEVICE CONTROL REGISTER..................................................................................... 61 
F
IGURE  3-8:  DEVICE STATUS REGISTER........................................................................................ 62 
FIGURE  3-9:  LINK CAPABILITIES REGISTER................................................................................... 63 
F
IGURE  3-10:  LINK CONTROL REGISTER....................................................................................... 64 
F
IGURE  3-11:  LINK STATUS REGISTER.......................................................................................... 65 
F
IGURE  4-1:  ADVANCED ERROR REPORTING EXTENDED CAPABILITY STRUCTURE ...................... 77 