滤波器设计.v

timescale 1ns 10ps module dec fit clk4x hsin vsin rin gin bin cntrl yout p uout p vout p yout n uout n vout n hsout vsout tout clk2x clk1x ; input clk4x clk2x clk1x; input [7:0] rin gin bin; input hsin vsin; input [8:0] cntrl; output [7:0] yout p uout p vout p; output [7:0] yout n uout n vout n; output hsout vsout; output [15:0] tout; wire dec1 byps cntrl[0]; wire dec2 byps cntrl[1]; wire clr sp byps cntrl[2]; wire negative en cntrl[7]; wire enable wen cntrl[8]; wire [3:0] test sel; assign test sel cntrl[6:3]; reg hs1 hs2 hs3 hs4; reg hrst1 hrst2 "> timescale 1ns 10ps module dec fit clk4x hsin vsin rin gin bin cntrl yout p uout p vout p yout n uout n vout n hsout vsout tout clk2x clk1x ; input clk4x clk2x clk1x; input [7:0] rin gin bin; input hsin vsin; input [8:0] cntrl; output [7:0] yout p uout p vout p; outpu [更多]