xilinx-zcu102-PS端PCIE接口配置调试（基于petalinux）

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Xilinx Answer 76169 1

Xilinx Answer 76169

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Overview

This document shows how to configure the Zynq UltraScale+ MPSoC Controller for PCI Express as

root complex, on a ZCU102 board, with an Intel SSD 750 Series NVMe (nonvolatile memory

endpoint) device as an endpoint. The document also walks through the steps to generate a PetaLinux

image to boot Linux on the Zynq UltraScale+ MPSoC.

Root Complex Design Overview

Figures below show the IP Integrator block design for the ZCU102 evaluation board with PCI Express

set up as root complex in PS-PCIe.

Figure 1 – Zynq UltraScale+ PS IP instantiated in IP Integrator

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Xilinx Answer 76169 2

© Copyright 2020 Xilinx

Xilinx Answer 76169 3

Figure 4 – PCIe IP configuration Root Port, link speed and MPS etc.

Figure 5 – Verify PCIe reference clock configuration

Figure 6 – Save and Validate the block design.