tms320vc5509a.pdf

所需积分/C币:9 2019-07-24 13:53:13 2.04MB PDF
11
收藏 收藏
举报

TMS320VC5509A Fixed-Point Digital Signal Processor Data Manual,5509A datasheet
Revision histor REVISION HISTORY This revision history highlights the technical changes made to SPRS205J to generate SPRS205K PAGES) ADDITION S/CHANGES/DELETIONS NO Table 2-3, Signal Descriptions(Continued Updated/changed D[15: 0] FUNCTION description from". The data bus keepers are disabled at re The data bus keepers are enabled at reset November 2002- Revised January 2008 ↓正xA5 SPRS205K INSTRUMENTS Revision History SPRS205K TEXAS November 2002- Revised January 2008 INSTRUMENTS Contents Contents Section Page TMS320VC5509A Features 2 Introduction,,,,,,,,,,,,,,,,,, 2.1 Description 2.2 Pin Assignments 2.2.1 Terminal Assignments for the GHH and ZHH Packages 2.2.2 Pin Assignments for the PGE Package 2.3 Signal Descriptions 3 Functional overview 1 Memory 32 3.1.1 On-Chip Dual-Access RAM(DARAM) 32 3.1.2 On-Chip Single-Access RAM (SARAM) 32 3.1.3 On-Chip Read-Only Memory(ROM) 33 3.1.4 Memory Map 3.1.5 Boot Configuration 36 3.2 Peripherals 37 3.3 Direct Memory Access(DMA) Controller 37 3.3.1 DMA Channel Control Register(DMA CCR) 38 3.4 2C Interface 39 3.5 Configurable External Buses 39 3.5.1 External Bus Selection Register(EBSR) 3.5.2 Parallel port 42 3.5.3 Parallel Port Signal routing 43 3.54seia| Ports,.,,,,,,,,,,,,, 45 3.6 General-Purpose Input/Output (GPIO)Ports 46 3.6.1 Dedicated General-Purpose 1/0 46 3.6.2 Address Bus General-Purpose 1/0 3.6.3 EHPI General-Purpose 1/O 49 3.7 System Regi 51 3. 8 USB Clock Generati 3.9 Memory-Mapped Registers 54 3.10 Peripheral Register Descriptio 56 3.11 Interrupts 3.11.1 FR and lER Registers 3.11.2 Interrupt Timing 3.11.3 Waking Up From IDLE Condition 76 3.11.4 Idling Clock Domain When EXternal Parallel Bus Operating in EHPI Mode 4 Support∴.∴. 画看画 4.1 Notices Concerning JTAG(IEEE 1149.1)Boundary Scan Test Capability 4.1.1 Initialization Requirements for Boundary Scan Test 4.1.2 Boundary Scan Description Language(BSDL)Model November 2002- Revised January 2008 EXAS SPRS205K INSTRUMENTS Contents ection age 4.2 Documentation Support 4.3 Device and Development-Support Tool Nomenclature 4. 4 TMS320VC5509A Device Nomenclature 5 Electrical Specifications 80 5. 1 Absolute Maximum Ratings 80 5.2 Recommended Operating Conditions 5.2.1 Recommended Operating Conditions for CVDD=1.2 V(108 MHz) 8 5.2.2 Recommended Operating Conditions for CVDD =1.35 V (144 MHz) 5.2.3 Recommended Operating Conditions for CVDD =1.6V(200 MHz) 83 5.3 Electrical Characteristics 5.3.1 Electrical Characteristics Over Recommended operating case temperature Range for CVdd =1.2V(108 MHz) 4 5.3.2 Electrical Characteristics over Recommended operating case Temperature Range for CVDD =1.35V(144 MHz) :: 8 5.3.3 Electrical Characteristics Over Recommended Operating Case Temperature Range for CVDD =1.6V(200 MHz) 5.4 ESD Performance 5.5 Timing Parameter Symbology 画11111 5.6 Clock Options 88 5.6.1 Internal System Oscillator With EXternal Crystal 5.6.2 Layout Considerations 89 56.3 Clock Generation in Bypass Mode(DPLL Disabled) 90 5.6.4 Clock Generation in Lock Mode(DPLL Synthesis Enabled) 5.6.5 Real-Time Clock Oscillator With EXternal Crystal 92 5.7 Memory Interface Timings 93 5.7.1 Asynchronous Memory Timings 5.7.2 Synchronous DRAM (SDRAM)Timings 96 5.8 Reset Timings 104 5.8.1 Power-Up Reset(On-Chip Oscillator Active) 104 5.8.2 Power-Up Reset(On-Chip Oscillator Inactive) 105 58.3 Warm Reset 106 5.9 External Interrupt Timings 107 5. 10 Wake-Up From IDLE 107 5. 11 XF Timings :.:.. 108 5. 12 General-Purpose Input/Output(GPlOx)Timings 109 5.13 TIN/TOUT Timings(TimerO Only 110 5.14 Multichannel Buffered serial Port (McBSP)Timings 5. 14.1 McBSPO Timings 5.14.2 McBSP1 and McBSP2 Timings 113 5.14.3 McBSP as SPI Master or Slave Timings 5. 14.4 McBSP General-Purpose /0 Timings 124 5. 15 Enhanced Host-Port Interface(EHPI)Timings 125 5.16 2C Timings 131 5.17 MultiMedia Card(MMC)Timings 134 5.18 Secure Digital(SD)Card Timings 135 5.19 Universal Serial Bus(USB) Timings 136 5.20 ADC Timings 138 6 SPRS205K TEXAS November 2002- Revised January 2008 INSTRUMENTS Contents Section ge 6 Mechanical data 139 6.1 Package Thermal Resistance Characteristics 139 6.2 Packaging Information 139 November 2002- Revised January 2008 EXAS SPRS205K INSTRUMENTS Figures List of Figures Fiqure 尸age 2-1 179-Terminal GHH and ZHH Ball Grid Array(Bottom View) 2-2 144-Pin PGE LoW-Profile Quad Flatpack(Top View) 3-1 Block Diagram of the TMS320VC5509A 3-2 TMS320VC5509A Memory Map(PGE Package) 3-3 TMS320VC5509A Memory Map(Ghh and ZHH Packages 35 3-4 DMA CCR Bit locations 38 3-5 EXternal Bus Selection Register 40 3-6 Parallel Port Signal Routing 43 3-7 Parallel Port(EMIF)Signal Interface 3-8 0 Direction Register(IODIR) Bit Layout 46 3-9 0 Data Register(IODaTA) Bit Layout 3-10 Address/GPIO Enable Register (AGPIOEN) Bit Layout 47 3-11 Address/GPIO Direction Register(AGPlodiR) bit layout 48 3-12 Address/GPIO Data Register(AGPIODATA) Bit Layout 48 3-13 EHPI GPIO Enable Register(EHPIGPIOEN) Bit Layout 49 3-14 EHPI GPIO Direction Register(EHPIGPlODIR) Bit Layout 49 3-15 EHPI GPIO Data Register(EHPIGPIODATA) Bit Layout 50 3-16 System Register Bit Locations 51 3-17 USB Clock Generation 3-18 USB PLL Selection and Status Register Bit Layout 52 3-19 USB APLL Clock Mode Register Bit Layout 3-20 FRO and iero Bit locations 3-21 FR1 and er1 Bit locations 4-1 Device nomenclature for the tms320VC5509A 79 5-13.3-V Test Load circuit 5-2 Internal System Oscillator With External Crystal 88 5-3 Bypass Mode Clock Timings 5-4 External Multiply-by-N Clock Timings Q 5-5 Real-Time Clock Oscillator With External Crystal 92 5-6 Asynchronous Memory Read Timings 5-7 Asynchronous Memory Write Timings 99 4=57 5-8 Three sDrAM Read commands 5-9 Three sDRAM wrt commands 98 5-10 SDRAM ACTV Command 99 5-11 SDRAM DCAB Command 100 5-12 SDRAM REFR Command 101 8 SPRS205K TEXAS November 2002- Revised January 2008 INSTRUMENTS Figures Figure ge 5-13 SDRAM MRS Command 102 5-14 SDRAM Self-Refresh command 103 5-15 Power-Up Reset(On-Chip Oscillator Active)Timings 104 5-16 Power-Up Reset(On-Chip Oscillator Inactive) Timings 105 5-17 Reset Timings 106 5-18 External Interrupt Timings 107 5-19 Wake-Up From IDLE Timings 107 5-20 XF Timings 108 5-21 General-Purpose Input/Output(IOx) Signal Timings 109 5-22 TIN/TOUT Timings When Configured as Inputs 110 5-23 TIN/TOUT Timings When Configured as Outputs 110 5-24 McBSP Receive Timings 115 5-25 McBSP Transmit Timings 115 5-26 McBSP Timings as SPI Master or Slave: CLKSTP =10b, CLKXP=0 5-27 McBSP Timings as SPI Master or Slave: CLKSTP=11b, CLKXP=0 119 5-28 McBSP Timings as spl master or slave: CLKSTP= 10b, CLKXP=1 121 5-29 MCBSP Timings as SPl Master or Slave: CLKSTP=11b, CLKXP=1 123 5-30 McBSP General-Purpose I/O Timings 124 5-31 HINT Timings 126 5-32 EHPI Nonmultiplexed Read/Write Timings 126 5-33 EHPI Multiplexed Memory(HPID)Read/Write Timings Without Autoincrement................127 5-34 EHPI Multiplexed Memory(HPID)Read Timings With Autoincrement 128 5-35 EHPI Multiplexed Memory(HPID) Write Timings with Autoincrement 129 5-36 EHPI Multiplexed Register Read/rite Timings 130 5-37 12C Receive Timings 132 5-38 2C Transmit Timings 133 5-39 MultiMedia Card(MMC) Timings 134 5-40 Secure Digital (SD)Timings 135 5-41 USB Timings 136 5-42 Full-Speed Loads 137 November 2002- Revised January 2008 EXAS SPRS205K INSTRUMENTS Tables List of tables Table 尸age Pin assignments for the ghh and zhh Packages 16 2-2 Pin Assignments for the PGE Package 2-3 Signal Descriptions 19 3-1 DARAM Blocks 3-2 SARAM Blocks 32 3-3 Boot Configuration Summary 36 3-4 Synchronization control Function 38 3-5 External Bus selection Register bit Field description 3-6 TMS320VC5509A Parallel Port Signal Routing 42 3-7 TMS320VC5509A Serial Port1 Signal Routing 45 3-8 TMS320VC5509A Serial Port2 Signal Routing 45 3-9 O Direction Register(ODR) Bit Functions∴∴ 46 3-10 0 Data Register (IODATA) Bit Functions 47 3-11 Address/GPIO Enable Register(AGPIOEN) Bit Functions 47 3-12 Address/GPIO Direction Register(AGPlODIR) Bit Functions 3-13 Address/GPIO Data Register(AGPIODATA) Bit Functions 48 3-14 EHPI GPlO Enable Register(EHPIGPIOEN)Bit Functions 3-15 EHPI GPlO Direction Register(EHPIGPIODIR) Bit Functions 4 3-16 EHPI GPIO Data Register(EHPIGPIODATA) Bit Functions 50 3-17 System Register Bit Fields 51 3-18 USB PLL Selection and Status Register Bit Functions 52 3-19 USB APLL Clock Mode Register Bit Functions 5 3-20 M and d values based on mode div and K 53 3-21 CPU Memory-Mapped Registers 3-22 Idle Control, Status, and System Registers 56 3-23 External m Registers 3-24 DMA Configuration Registers 57 3-25 Real-Time Clock Registers 63 3-26 Clock Generator 63 3-27 Timers 63 3-28 Multichannel serial Port #0 64 3-29 Multichannel Serial Port #1 65 3-30 Multichannel serial port #t2 3-31GP|o. 67 3-32 Device revision D 67 3-33 [2C Module Registers 67 3-34 Watchdog Timer Registers 68 3-35 MMC/SD1 Module registers 68 3-36 MMC/SD2 Module Registers 3-37 USB Module Registers 3-38 Analog-to-Digital Controller(ADC) Registe/o 3-39 EXternal Bus Selection Register 3-40 Interrupt Table 73 3-41 IFRO and IERO Register Bit Fields 3-42 FR1 and IER1 Register Bit Fields 10 SPRS205K TEXAS November 2002- Revised January 2008 INSTRUMENTS

...展开详情
试读 127P tms320vc5509a.pdf
立即下载
限时抽奖 低至0.43元/次
身份认证后 购VIP低至7折
一个资源只可评论一次,评论内容不能少于5个字
您会向同学/朋友/同事推荐我们的CSDN下载吗?
谢谢参与!您的真实评价是我们改进的动力~
上传资源赚钱or赚积分
最新推荐
tms320vc5509a.pdf 9积分/C币 立即下载
1/127
tms320vc5509a.pdf第1页
tms320vc5509a.pdf第2页
tms320vc5509a.pdf第3页
tms320vc5509a.pdf第4页
tms320vc5509a.pdf第5页
tms320vc5509a.pdf第6页
tms320vc5509a.pdf第7页
tms320vc5509a.pdf第8页
tms320vc5509a.pdf第9页
tms320vc5509a.pdf第10页
tms320vc5509a.pdf第11页
tms320vc5509a.pdf第12页
tms320vc5509a.pdf第13页
tms320vc5509a.pdf第14页
tms320vc5509a.pdf第15页
tms320vc5509a.pdf第16页
tms320vc5509a.pdf第17页
tms320vc5509a.pdf第18页
tms320vc5509a.pdf第19页
tms320vc5509a.pdf第20页

试读结束, 可继续阅读

9积分/C币 立即下载