User’s Manual
PowerPC 405-S Embedded Processor Core
Contents
Page 4 of 557
Version 1.2
June 16, 2010
2.3.3 Link Register .......................................................................................................................... 43
2.3.3.1 Fixed-Point Exception Register ..................................................................................... 43
2.3.3.2 Special Purpose Register General (SPRG0 - SPRG7) .................................................. 45
2.3.3.3 Processor Version Register ............................................................................................ 46
2.3.4 Condition Register ................................................................................................................. 46
2.3.4.1 CR Fields after Comparison Instructions ........................................................................ 47
2.3.4.2 The CR0 Field ................................................................................................................ 48
2.3.5 The Time Base ....................................................................................................................... 49
2.3.6 Machine State Register .......................................................................................................... 49
2.3.7 Device Control Registers ....................................................................................................... 51
2.4 Data Types and Alignment .............................................................................................................. 51
2.4.1 Alignment for Storage Reference and Cache Control Instructions ........................................ 52
2.4.2 Alignment and Endian Operation ........................................................................................... 52
2.4.3 Summary of Instructions Causing Alignment Exceptions ...................................................... 52
2.5 Byte Ordering ................................................................................................................................. 53
2.5.1 Structure Mapping Examples ................................................................................................. 54
2.5.1.1 Big-Endian Mapping ....................................................................................................... 54
2.5.1.2 Little-Endian Mapping ..................................................................................................... 55
2.5.2 Support for Little-Endian Byte Ordering ................................................................................. 55
2.5.3 Endian (E) Storage Attribute .................................................................................................. 55
2.5.3.1 Fetching Instructions from Little-Endian Storage Regions ............................................. 55
2.5.3.2 Accessing Data in Little-Endian Storage Regions .......................................................... 56
2.5.3.3 PowerPC Byte-Reverse Instructions .............................................................................. 57
2.6 Instruction Processing ..................................................................................................................... 59
2.7 Branch Processing .......................................................................................................................... 60
2.7.1 Unconditional Branch Target Addressing Options ................................................................. 60
2.7.2 Conditional Branch Target Addressing Options ..................................................................... 60
2.7.3 Conditional Branch Condition Register Testing ..................................................................... 61
2.7.4 BO Field on Conditional Branches ......................................................................................... 61
2.7.5 Branch Prediction ................................................................................................................... 62
2.8 Speculative Accesses ..................................................................................................................... 63
2.8.1 Speculative Accesses in the PowerPC 405-S ....................................................................... 64
2.8.1.1 Prefetch Distance Down an Unresolved Branch Path .................................................... 64
2.8.1.2 Prefetch of Branches to the CTR and Branches to the LR ............................................. 64
2.8.2 Preventing Inappropriate Speculative Accesses .................................................................... 65
2.8.2.1 Fetching Past an Interrupt-Causing or Interrupt-Returning Instruction ........................... 65
2.8.2.2 Fetching Past tw or twi Instructions ................................................................................ 66
2.8.2.3 Fetching Past an Unconditional Branch ......................................................................... 66
2.8.2.4 Suggested Locations of Memory-Mapped Hardware ..................................................... 66
2.8.3 Summary ................................................................................................................................ 67
2.9 Privileged Mode Operation .............................................................................................................. 67
2.9.1 MSR Bits and Exception Handling ......................................................................................... 67
2.9.2 Privileged Instructions ............................................................................................................ 68
2.9.3 Privileged SPRs ..................................................................................................................... 68
2.9.4 Privileged DCRs ..................................................................................................................... 69
2.10 Synchronization ............................................................................................................................. 69
2.10.1 Context Synchronization ...................................................................................................... 69
2.10.2 Execution Synchronization ................................................................................................... 72
2.10.3 Storage Synchronization ...................................................................................................... 72
评论0