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Errata Notice
PowerPC 405-S Embedded Processor Core
Version 1.0
June 16, 2008 - IBM Confidential
Page 1
Introduction
This document describes errata and provides design notes that affect designs using the IBM PowerPC® 405-
S Embedded Processor Core. Each erratum includes an overview, a description of the system impact, and a
description of possible workarounds. Design notes cover items that are not considered errata, but need a
description beyond what is provided in the published documentation.
Table 1 on page 2 identifies errata
affecting cores by version. Table 2 on page 2 and Table 3 on page 3 contain a summary of all errata and
design notes.
Errata are listed in numeric order. Gaps in the numeric sequence are intentional; only applicable items are
included in this document.
Category Definitions
Errata are classified according to system impact and availability of a workaround.
1. Major impact; no workaround is available. A problem is said to have a major impact if it results in a system
crash, a hard failure, an unrecoverable soft failure, significant performance degradation, or the storage of
incorrect data.
2. Major impact; a workaround is impractical to implement, or a substantial risk of encountering the same or
additional problems, including performance issues, exists after the workaround is implemented.
3. Major impact; a workaround is available. Application of the workaround either eliminates the problem, or
reduces it to a minor impact issue.
4. Minor impact; no workaround is available. Minor impact problems result in slight to moderate performance
degradation, or are a functional variance from specification.
5. Minor impact; a workaround is available. Minor impact problems result in slight to moderate performance
degradation, or are a functional variance from specification.
6. Design enhancement.
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Errata Notice
PowerPC 405-S Embedded Processor Core
Page 2
Version 1.0
June 16, 2008 - IBM Confidential
Errata Summary
Table 1. List of All Errata and Cores Affected
Errata 405-S Embedded Processor Core
CPU_121 X
CPU_147 X
CPU_153 X
CPU_162 X
CPU_163 X
CPU_187 X
CPU_197 X
CPU_208 X
CPU_212 X
Table 2. Errata Summary
Errata Category Description
Date First
Documented
Date Last
Updated
CPU_121
3 The iccci instruction may errantly cause a Data TLB Exception. 4/19/99 4/19/99
CPU_147 3 Virtual memory marked as nonexecutable storage (storage attribute
EX
= 0) can be loaded into the instruction cache using the icbt instruction.
8/12/99 4/27/00
CPU_153 5 Floating-point enabled exceptions do not update the CR1 field of the CR.
9/13/99 4/26/00
CPU_162
3 When in real mode, the PowerPC 405-S Embedded Processor Core may
errantly make speculative instruction fetches from guarded storage.
1/7/00 2/24/00
CPU_163
3 Floating-point enabled exception handlers cannot reliably determine if
SRR0 points to the excepting instruction.
1/17/00 4/26/00
CPU_187
5 Access to guarded storage via APU load/store doubleword or APU
load/store quadword instructions is not architecturally compliant.
4/12/00 5/10/00
CPU_197
3 Incorrect real mode attributes may be used when accessing the last
instruction in a 128 MB region.
11/17/00 11/17/00
CPU_208
3 icbt instructions executed with data relocation enabled may cause
incorrect instruction execution if the icbt misses in the UTLB or does not
have permission to access the page.
8/21/01 8/21/01
CPU_212
3
When attached to a multicycle OCM controller, the PowerPC 405-S
Embedded Processor Core may assert the C405_dsocmWait signal
during the assertion of DSOCM_c405Hold or DSOCM_c405Complete for
an OCM store operation. The PowerPC 405-S Embedded Processor Core
ignores a valid DSOCM_c405Complete signal for an OCM store while
asserting C405_dsocmWait.
9/27/02 10/18/02
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Errata Notice
PowerPC 405-S Embedded Processor Core
Version 1.0
June 16, 2008 - IBM Confidential
Page 3
Design Note Summary
Table 3. Design Note Summary
Item Description
Date First
Documented
Date Last
Updated
1 PowerPC 405 Core Support Manuals prior to the March 2003 publication contain an error
in the 2-cycle OCM control example in section 2.11.5.
May 9, 2003 May 9, 2003
2 The PowerPC 405F5V2 is a functionally equivalent replacement of the PowerPC
405F5V1 with improvements to PLB synchronization logic. The improved timing simplifies
timing closure.
April 5, 2004 April 5, 2004
3 Functional, system, and application mode use of the CPU Clock Enable pin
(CPM_c405CpuClkEn_lssdCClk) is no longer supported. An alternate method must be
used to provide for active power management. Use of this pin for LSSD test function is
still supported and required.
November 26,
2007
November 26,
2007
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Errata Notice
PowerPC 405-S Embedded Processor Core
Page 4
Version 1.0
June 16, 2008 - IBM Confidential
CPU_121
Abstract: The iccci instruction may errantly cause a Data TLB Exception.
Category: 3 Major impact; a workaround is available. Application of the workaround either elim-
inates the problem, or reduces it to a minor impact issue.
Overview
When data-side relocation (data address translation) is enabled (MSR[DR] = 1), an iccci instruction errantly
attempts an access check for the associated page. Since an iccci instruction invalidates the entire instruction
cache, the effective address it generates is unnecessary.
Impact
When data-side relocation (data address translation) is enabled, the execution of an iccci instruction may
cause a Data TLB miss exception.
Workaround
There are two possible workarounds. Workaround 1 avoids this erratum by temporarily disabling data
address translation. Workaround 2 describes how to handle this erratum without disabling data address
translation.
1. Before executing an iccci instruction, make sure the MSR[DR] is disabled. This can be done using the
following pseudo code:
mfmsr Rx ! Rx is a scratch reg
andi Ry,Rx,DR_MASK ! clear MSR[DR] in scratch reg Rx
mtmsr Ry
isync
iccci 0,Rx ! The address does not matter.
mtmsr Rx
isync
2. When data-side relocation is enabled, ensure that the virtual address generated by the iccci (virtual
address = {PID, effective address (RA | 0 + RB)}) has a corresponding page in the TLB.
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