USB Function
IP Core
Author: Rudolf Usselmann
rudi@asics.ws
www.asics.ws
Rev. 1.5
January 27, 2002
OpenCores USB Function Core January 27, 2002
www.opencores.org Rev. 1.5 1 of 63
Revision History
Rev. Date Author Description
0.1 6/1/01 Rudolf
Usselmann
First Draft
0.4 10/1/01 RU Dropped the linked list for endpoints idea, removed the buffer.
shared bit, added and modified registers.
Added Appendix B: Configuring the Core.
0.5 11/1/01 RU Changed buffer memory to a dual ported SSRAM.
Added quadruple buffering.
Filled in CSR register.
Added size field to end point buffers.
0.6 13/1/01 RU Added Change bars.
Changed buffer memory back to single port SSRAM.
Removed quadruple buffering (back to double buffering).
Enhanced the way buffers work, added description.
Added data organization section.
Added various references to latency and bandwidth requirements.
Added USB core behavior section.
0.7 15/1/01 RU Added frame number and time (FRM_NAT) register.
Filled in USB core behavior section.
Filled in most of the flowcharts.
Fixed endpoint interrupt register.
Added suspend output to wishbone IF.
Added names to some of the bits in the endpoint registers.
0.8 20/1/01 RU Changed document format to double sided.
Added Suspend and Resume Interrupts.
Added RX control of packet that are not MAX_PL_SZ.
Added vendor control IO port register and IOs.
Added Setup description.
0.9 31/1/01 RU Added DMA operations and signals.
Added separate core selects for registers and buffer memory.
0.9b 20/2/01 RU Some minor typing fixes.
Added a brief discussion about PID sequencing.
Modified the interrupts.
Modified the WISHBONE interface.
1.0 28/2/01 RU Added Buffer Overflow & Underflow descriptions.
Changed clock domain separation (Figure 1).
Removed document status “Preliminary Draft”.
1.1 7/3/01 RU Added USB device control flow charts.
Gave Names to Endpoint Registers.
Added Interrupt Section.
Added Suspend & Resume Section.
Added Appendix C: USB Core Structure.
Made various grammar and syntax corrections.
January 27, 2002 USB Function Core OpenCores
2 of 63 Rev. 1.5 www.opencores.org
1.2 30/3/01 RU Rearranged Appendixes.
Moved Buffer Memory (SSRAM) outside the core.
Added Appendix describing SSRAM timing.
Filled in Core Configuration Appendix.
Modified DMA Operations section.
Added OTS_STOP bit in endpoint CSR register.
Added “OUT is smaller than MAX_PL_SZ” interrupt.
Fixed addresses of registers.
1.3 30/5/01 RU Fixed many syntax and grammar errors.
Removed Software model Section.
Added Appendix E: Software model, provided by Chris Ziomkowski
(chris@asics.ws).
1.4 10/8/01 RU - Changed IO names to be more clear.
- Uniquifyed define names to be core specific.
1.5 26/1/02 RU - Added more detailed descriptions and clarifications.
Rev. Date Author Description
OpenCores USB Function Core January 27, 2002
www.opencores.org Rev. 1.5 3 of 63
1
Introduction
The Universal Serial Bus (USB) has evolved to the standard interconnect
between computers and peripherals. Everything from a mouse to a camera can be
connected via USB. With the new USB 2.0 specification, data rates of over 480
Mb/s are possible.
The Universal Serial Bus is a point to point interface. Multiple peripherals are
attached through a HUB to the host.
This core provides a function (peripheral device) interface. It can be used to
interface almost any peripheral to a computer via USB. This core fully complies to
the USB 2.0 specification and can operate at USB Full and High Speed rates (12
and 480 Mb/s).
Note:
This specification assumes that the core will most likely be used in a high
speed environment and includes references to special high speed exten-
sions. However, when operation in full speed mode only, some of those
high speed extensions will not be used and the core will properly behave as
a full speed function only.
