852 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 5, MAY 2004
A Low-Power ASIC Design for Cell Search in the W-CDMA System
Chi-Fang Li, Student Member, IEEE, Yuan-Sun Chu, Wern-Ho Sheen, Member, IEEE, Fu-Chin Tian, and
Jan-Shin Ho, Student Member, IEEE
Abstract—This paper presents a low-power ASIC design for cell
search in the wideband code-division multiple-access (W-CDMA)
system. A low-complexity algorithm that is able to work satisfac-
torily under the effect of large frequency and clock errors is de-
signed first. Then, a set of low-power measures are employed in
the design of hardware architecture and circuits. Finally, through
power analysis, critical blocks are identified and redesigned so as
to further reduce the power consumption. The final design shows
that the power is reduced by 51% from the original design of 133.6
mW to 65.49 mW, and its core area is also reduced by 31.9% from
3 4 3 4
mm
2
to
2 8 2 8
mm
2
. The design is implemented
and verified in a 3.3-V 0.35-
m CMOS technology with clock rate
15.36 MHz.
Index Terms—Cell search, clock error, frequency error,
low-power design, W-CDMA.
I. INTRODUCTION
I
N A CODE-DIVISION multiple-access (CDMA) cellular
system, the procedure employed by a mobile station to
search for the best cell site and to achieve code, time, and fre-
quency synchronization with it is referred to as cell search. Fast
cell search is particularly important for the wideband CDMA
(W-CDMA) system because of the use of nonsynchronous base
stations in the system [1], [2].
A three-stage search procedure has been designed in the
W-CDMA specifications in order to facilitate fast cell search,
including slot synchronization, joint frame synchronization
and code-group identification, and scrambling-code detection
[2]. Slot synchronization (stage 1) is achieved by detecting
the primary synchronization channel (PSCH). Joint frame
synchronization and code-group identification (stage 2) is
achieved by detecting the secondary synchronization channel
(SSCH). And, after the code group is identified, the scrambling
code can be determined easily by using the common pilot
channel (CPICH) (stage 3).
A great deal of research has been contributed to the design of
the cell search algorithms [1], [3]–[5]. In [1], a pipelined process
was proposed to achieve faster cell search than the serial one
at the cost of higher complexity. Partial symbol de-spreading
with noncoherent combining was proposed in [1], [3] to over-
come large frequency error due to the oscillator inaccuracy of
Manuscript received March 6, 2003; revised December 15, 2003. This work
was supported by the Chip Implementation Center, National Science Council,
under Grant NSC92-2218-E-194-008.
C.-F. Li, Y.-S. Chu, F.-C. Tian, and J.-S. Ho are with the Department of Elec-
trical Engineering, National Chung-Cheng University, Chia-Yi 621, Taiwan,
R.O.C. (e-mail: richard@vlsi.ee.ccu.edu.tw).
W.-H. Sheen is with the Department of Communication Engineering,
National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail:
whsheen@cm.nctu.edu.tw).
Digital Object Identifier 10.1109/JSSC.2004.826337
a mobile station. This imperfection also incurs sampling error
(clock error) at the analog-to-digital converter (ADC). It was
shown in [4] that the clock error may exceed over one timing
period during the course of three-stage search and that will re-
sult in search failure. In [5], a search scheme with multiple “code
time” candidates was proposed to reduce the search time in the
clock-drifting environment.
In this paper, a low-power ASIC is designed for cell search
in the W-CDMA system under the effect of large frequency
and clock errors. A set of low-power design practices starting
from the algorithm to hardware architecture and circuits is per-
formed so as to reduce chip’s power consumption. By using the
power-efficient algorithm, architecture, and circuit designs, the
power consumption of the design is reduced by 51%. The de-
sign is implemented and verified in a 3.3-V 0.35-
m CMOS
technology with clock rate 15.36 MHz.
The rest of this paper is organized as follows. Section II
presents a low-complexity cell search algorithm under large
frequency and clock errors. Section III describes low-power
architecture and circuits, power analysis, and redesign of
critical blocks. Section IV summarizes implementation and
testing results. Finally, the paper is concluded in Section V.
II. L
OW-COMPLEXITY CELL SEARCH ALGORITHM
Three stages of cell search can be performed either in the se-
rial or pipelined fashion [1]. In the pipelined search, all three
stages are performed concurrently and that results in a faster
search. In this paper, a low-complexity pipelined search algo-
rithm will be adopted for the low-power ASIC design.
Different methods have been proposed to counteract the
effects of frequency and clock errors on the cell search perfor-
mance. Generally, two methods can be used to mitigate the effect
of large frequency error. One is frequency offset compensation
(FOC) and the other is partial symbol spreading (PSD). FOC
has superior performance but needs multiple stage-1 detectors
[1], [4]. To counteract the clock error, the simplest method
is the random sampling per frame (RSPF) proposed in [4],
which was shown to be able to work satisfactorily under 4 ppm
of clock error. For large clock error, the method of multiple
timing candidates (MTC) could be employed, but multiple
stage-2 and stage-3 detectors are needed [5]. Here, a simple
method called sample-point reordering (SPR) is proposed to
counteract the clock error for up to 10 ppm. The basic idea
is as follows. First, the range of clock error is divided into
“bins” with each bin denoting a presumed clock error. Then,
within a bin, a controller is used to drop or stuff one sample
point from or into incoming sampled sequence whenever the
0018-9200/04$20.00 © 2004 IEEE
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