PHY Interface for the PCI Express, SATA,
and USB 3.10 Architectures
©2007 - 2013, 2008, 2009 Intel Corporation—All rights reserved. Page 4 of 90
Table of Contents
1 Preface ...................................................................................................................................... 7
1.1 Scope of this Revision ...................................................................................................... 7
1.2 Revision History ............................................................................................................... 7
2 Introduction .............................................................................................................................. 9
2.1 PCI Express PHY Layer ................................................................................................. 11
2.2 USB PHY Layer ............................................................................................................. 11
2.3 SATA PHY Layer ........................................................................................................... 12
3 PHY/MAC Interface .............................................................................................................. 12
4 PCI Express and USB PHY Functionality ............................................................................. 16
4.1 Transmitter Block Diagram (2.5 and 5.0 GT/s) .............................................................. 17
4.2 Transmitter Block Diagram (8.0/10 GT/s) ...................................................................... 17
4.3 Receiver Block Diagram (2.5 and 5.0 GT/s) .................................................................. 18
4.4 Receiver Block Diagram (8.0/10.0 GT/s) ....................................................................... 19
4.5 Clocking .......................................................................................................................... 20
5 SATA PHY Functionality ...................................................................................................... 20
5.1 Transmitter Block Diagram (1.5, 3.0, and 6.0 GT/s) ..................................................... 21
5.2 Receiver Block Diagram (1.5, 3.0 and 6.0 GT/s) ........................................................... 22
5.3 Clocking .......................................................................................................................... 22
6 PIPE Interface Signal Descriptions ........................................................................................ 23
6.1 PHY/MAC Interface Signals .......................................................................................... 23
6.2 External Signals .............................................................................................................. 49
7 PIPE Operational Behavior .................................................................................................... 51
7.1 Clocking .......................................................................................................................... 51
7.2 Reset ................................................................................................................................ 51
7.3 Power Management – PCI Express Mode ...................................................................... 52
7.4 Power Management – USB Mode .................................................................................. 54
7.5 Power Management – SATA Mode ................................................................................ 55
7.6 Changing Signaling Rate, PCLK Rate, or Data Bus Width ............................................ 56
7.6.1 PCI Express Mode ................................................................................................... 56
7.6.2 USB Mode ............................................................................................................... 56
7.6.3 SATA Mode ............................................................................................................ 57
7.6.4 Fixed data path implementations ............................................................................. 58
7.6.5 Fixed PCLK implementations ................................................................................. 58
7.7 Transmitter Margining – PCI Express Mode and USB Mode ........................................ 59
7.8 Selectable De-emphasis – PCI Express Mode ................................................................ 59
7.9 Receiver Detection – PCI Express Mode and USB Mode .............................................. 60
7.10 Transmitting a beacon – PCI Express Mode ............................................................... 61
7.11 Transmitting LFPS – USB Mode ................................................................................ 61
7.12 Detecting a beacon – PCI Express Mode .................................................................... 62
7.13 Detecting Low Frequency Periodic Signaling – USB Mode ....................................... 62
7.14 Clock Tolerance Compensation .................................................................................. 62
7.15 Error Detection ............................................................................................................ 64
7.15.1 8B/10B Decode Errors ............................................................................................. 65
7.15.2 Disparity Errors ....................................................................................................... 65
7.15.3 Elastic Buffer Errors ................................................................................................ 66
7.16 Loopback ..................................................................................................................... 67
7.17 Polarity Inversion – PCI Express and USBModes ...................................................... 69
7.18 Setting negative disparity (PCI Express Mode) .......................................................... 69
7.19 Electrical Idle – PCI Express Mode ............................................................................ 70
