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Design of the RISC-V Instruction Set Architecture
Andrew Waterman
Electrical Engineering and Computer Sciences
University of California at Berkeley
Technical Report No. UCB/EECS-2016-1
http://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-1.html
January 3, 2016
Copyright © 2016, by the author(s).
All rights reserved.
Permission to make digital or hard copies of all or part of this work for
personal or classroom use is granted without fee provided that copies are
not made or distributed for profit or commercial advantage and that copies
bear this notice and the full citation on the first page. To copy otherwise, to
republish, to post on servers or to redistribute to lists, requires prior specific
permission.
Design of the RISC-V Instruction Set Architecture
by
Andrew Shell Waterman
A dissertation submitted in partial satisfaction of the
requirements for the degree of
Doctor of Philosophy
in
Computer Science
in the
Graduate Division
of the
University of California, Berkeley
Committee in charge:
Professor David Patterson, Chair
Professor Krste Asanovi´c
Associate Professor Per-Olof Persson
Spring 2016
Design of the RISC-V Instruction Set Architecture
Copyright 2016
by
Andrew Shell Waterman
1
Abstract
Design of the RISC-V Instruction Set Architecture
by
Andrew Shell Waterman
Doctor of Philosophy in Computer Science
University of California, Berkeley
Professor David Patterson, Chair
The hardware-software interface, embodied in the instruction set architecture (ISA), is
arguably the most important interface in a computer system. Yet, in contrast to nearly all
other interfaces in a modern computer system, all commercially popular ISAs are proprietary.
A free and open ISA standard has the potential to increase innovation in microprocessor
design, reduce computer system cost, and, as Moore’s law wanes, ease the transition to more
specialized computational devices.
In this dissertation, I present the RISC-V instruction set architecture. RISC-V is a free
and open ISA that, with three decades of hindsight, builds and improves upon the original
Reduced Instruction Set Computer (RISC) architectures. It is structured as a small base ISA
with a variety of optional extensions. The base ISA is very simple, making RISC-V suitable
for research and education, but complete enough to be a suitable ISA for inexpensive, low-
power embedded devices. The optional extensions form a more powerful ISA for general-
purpose and high-performance computing. I also present and evaluate a new RISC-V ISA
extension for reduced code size, which makes RISC-V more compact than all popular 64-bit
ISAs.
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