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This is version 1.10 of the RISC-V privileged architecture proposal
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The RISC-V Instruction Set Manual
Volume II: Privileged Architecture
Privileged Architecture Version 1.10
Document Version 1.10
Warning! This draft specification may change before being accepted as
standard by the RISC-V Foundation. While the editors intend future changes
to this specification to be forward compatible, it remains possible that
implementations made to this draft specification will not conform to the future
standard.
Editors: Andrew Waterman
1
, Krste Asanovi´c
1,2
1
SiFive Inc.,
2
CS Division, EECS Department, University of California, Berkeley
andrew@sifive.com, krste@berkeley.edu
May 7, 2017
Contributors to all versions of the spec in alphabetical order (please contact editors to suggest
corrections): Krste Asanovi´c, Rimas Aviˇzienis, Jacob Bachmeyer, Allen J. Baum, Paolo Bonzini,
Ruslan Bukin, Christopher Celio, David Chisnall, Anthony Coulter, Palmer Dabbelt, Monte Dal-
rymple, Dennis Ferguson, Mike Frysinger, John Hauser, David Horner, Olof Johansson, Yunsup
Lee, Andrew Lutomirski, Jonathan Neusch¨afer, Rishiyur Nikhil, Stefan O’Rear, Albert Ou, John
Ousterhout, David Patterson, Colin Schmidt, Wesley Terpstra, Matt Thomas, Tommy Thorn, Ray
VanDeWalker, Megan Wachs, Andrew Waterman, and Reinoud Zandijk.
This document is released under a Creative Commons Attribution 4.0 International License.
This document is a derivative of the RISC-V privileged specification version 1.9.1 released under
following license:
c
2010–2017 Andrew Waterman, Yunsup Lee, Rimas Aviˇzienis, David Patterson,
Krste Asanovi´c. Creative Commons Attribution 4.0 International License.
Please cite as: “The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version
1.10”, Editors Andrew Waterman and Krste Asanovi´c, RISC-V Foundation, May 2017.
Preface
This is version 1.10 of the RISC-V privileged architecture proposal. Changes from version 1.9.1
include:
• The previous version of this document was released under a Creative Commons Attribution
4.0 International Licence by the original authors, and this and future versions of this document
will be released under the same licence.
• The explicit convention on shadow CSR addresses has been removed to reclaim CSR space.
Shadow CSRs can still be added as needed.
• The mvendorid register now contains the JEDEC code of the core provider as opposed to
a code supplied by the Foundation. This avoids redundancy and offloads work from the
Foundation.
• The interrupt-enable stack discipline has been simplified.
• An optional mechanism to change the base ISA used by supervisor and user modes has been
added to the mstatus CSR, and the field previously called Base in misa has been renamed
to MXL for consistency.
• Clarified expected use of XS to summarize additional extension state status fields in mstatus.
• Optional vectored interrupt support has been added to the mtvec and stvec CSRs.
• The SEIP and UEIP bits in the mip CSR have been redefined to support software injection
of external interrupts.
• The mbadaddr register has been subsumed by a more general mtval register that can now
capture bad instruction bits on an illegal instruction fault to speed instruction emulation.
• The machine-mode base-and-bounds translation and protection schemes have been removed
from the specification as part of moving the virtual memory configuration to sptbr (now
satp). Some of the motivation for the base and bound schemes are now covered by the PMP
registers, but space remains available in mstatus to add these back at a later date if deemed
useful.
• In systems with only M-mode, or with both M-mode and U-mode but without U-mode
trap support, the medeleg and mideleg registers now do not exist, whereas previously they
returned zero.
• Virtual-memory page faults now have mcause values distinct from physical-memory access
exceptions. Page-fault exceptions can now be delegated to S-mode without delegating excep-
tions generated by PMA and PMP checks.
• An optional physical-memory protection (PMP) scheme has been proposed.
• The supervisor virtual memory configuration has been moved from the mstatus register to
the sptbr register. Accordingly, the sptbr register has been renamed to satp (Supervisor
i
ii Volume II: RISC-V Privileged Architectures V1.10
Address Translation and Protection) to reflect is broadened role.
• The SFENCE.VM instruction has been removed in favor of the improved SFENCE.VMA
instruction.
• The mstatus bit MXR has been exposed to S-mode via sstatus.
• The polarity of the PUM bit in sstatus has been inverted to shorten code sequences involving
MXR. The bit has been renamed to SUM.
• Hardware management of page-table entry Accessed and Dirty bits has been made optional;
simpler implementations may trap to software to set them.
• The counter-enable scheme has changed, so that S-mode can control availability of counters
to U-mode.
• H-mode has been removed, as we are focusing on recursive virtualization support in S-mode.
The encoding space has been reserved and may be repurposed at a later date.
• A mechanism to improve virtualization performance by trapping S-mode virtual-memory
management operations has been added.
• The Supervisor Binary Interface (SBI) chapter has been removed, so that it can be maintained
as a separate specification.
Volume II: RISC-V Privileged Architectures V1.10 iii
Preface to Version 1.9.1
This is version 1.9.1 of the RISC-V privileged architecture proposal. Changes from version 1.9
include:
• Numerous additions and improvements to the commentary sections.
• Change configuration string proposal to be use a search process that supports various formats
including Device Tree String and flattened Device Tree.
• Made misa optionally writable to support modifying base and supported ISA extensions.
CSR address of misa changed.
• Added description of debug mode and debug CSRs.
• Added a hardware performance monitoring scheme. Simplified the handling of existing hard-
ware counters, removing privileged versions of the counters and the corresponding delta reg-
isters.
• Fixed description of SPIE in presence of user-level interrupts.
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