飞思卡尔P1010原理图
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2018-10-25
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D D
C C
B B
A A
Table of Contents
DDR
2 Notes
3
Revisions
Rev Description
X1 Original Release
Approved
T.Q
Date
June 29, 2010
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LOCAL BUS
CPU MISC & POR
ETHERNET PHY1 & 1588
ETHERNET PHY2-3
SATA & PCIE
PERIPHERALS
USB
CPLD
PORT
CPU POWER
P1010RDB
POWER SUPPLY (CPU)
POWER SUPPLY (MISC)
SLIC
A Formal Release A July 06, 2010 T.Q
A1 Formal Release A1 Sept 21, 2010 T.Q
A Release version for prototypeA
Initail Draft
Revision History
X1
Rev
A1 Change R342, R133 to DNP, populate R134
Change Y4, C57, C64, R100 to DNP
DDR3 Chip use standard 2Gbit symbol in schematic
Release version for prototypeB, it share same PCB with prototypeA
B
1. Add I2C chip(U71) and DIP SW6 to control bus switch and CS0,1 selection
2. Remove U43,U44,U45 address select for P1020 circuit
3. Add J34 to select 8bit or 16bit Nor flash
4. Remove POR resistors and 100MHz osc for P1020
5. Adjust switch signals location, let same functionality switches together
6. Connect J33 earth ground and signal ground together
7. Remove U50(Watchdog) and connect GPIO5,6,7 to CPLD.
Dec 17, 2010First Release BAX1
Dec 28, 2010B Formal Release B
B1 Formal Release B1 Feb 24, 2011
1. R511~R515 populated on.
2. R96 change to 75ohm.
B1
B2
1. Change DDR3 (U31~U34) to K4B2G0846C-HCH9 (1333MHz)
B2 Formal Release B2 May 30, 2011
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Networking & Multimedia Group
6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to Freescale Semiconductor and shall not be used for
engineering design, procurement or manufacture in whole or in part without the express written permission
of Freescale Semiconductor.
ICAP Classification: FCP: FIUO: PUBI:
SCH-26374 PDF: SPF-26374 B2
P1010RDB
C
Monday, May 30, 2011
COVER PAGE
PAUL GAN
PAUL GAN
1 16
____X____
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Networking & Multimedia Group
6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to Freescale Semiconductor and shall not be used for
engineering design, procurement or manufacture in whole or in part without the express written permission
of Freescale Semiconductor.
ICAP Classification: FCP: FIUO: PUBI:
SCH-26374 PDF: SPF-26374 B2
P1010RDB
C
Monday, May 30, 2011
COVER PAGE
PAUL GAN
PAUL GAN
1 16
____X____
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Networking & Multimedia Group
6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to Freescale Semiconductor and shall not be used for
engineering design, procurement or manufacture in whole or in part without the express written permission
of Freescale Semiconductor.
ICAP Classification: FCP: FIUO: PUBI:
SCH-26374 PDF: SPF-26374 B2
P1010RDB
C
Monday, May 30, 2011
COVER PAGE
PAUL GAN
PAUL GAN
1 16
____X____
R96原来为10欧姆
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soul_winds2019-08-09是P1010RDB的原理图
