axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,D:/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ip/top_processing_system7_0_0"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,D:/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ip/top_processing_system7_0_0"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,D:/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ip/top_processing_system7_0_0"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,D:/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ip/top_processing_system7_0_0"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"
axi_vip_pkg.sv,systemverilog,xilinx_vip,D:/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ip/top_processing_system7_0_0"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"
axi4stream_vip_if.sv,systemverilog,xilinx_vip,D:/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ip/top_processing_system7_0_0"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"
axi_vip_if.sv,systemverilog,xilinx_vip,D:/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ip/top_processing_system7_0_0"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"
clk_vip_if.sv,systemverilog,xilinx_vip,D:/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ip/top_processing_system7_0_0"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"
rst_vip_if.sv,systemverilog,xilinx_vip,D:/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/ec67/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/8c62/hdl"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ip/top_processing_system7_0_0"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/1ddd/hdl/verilog"incdir="../../../../project_DDR_IRQ.srcs/sources_1/bd/top/ipshared/b2d0/hdl/verilog"
xpm_cdc.sv,systemverilog,xil_defaultlib,D:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../project_DDR_IRQ.
ZYNQ FREERTOS PL中断测试
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2023-06-17
22:42:57
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ZYNQ FREERTOS PL中断测试 （1432个子文件） 
__synthesis_is_complete__ 0B __synthesis_is_complete__ 0B __synthesis_is_complete__ 0B __synthesis_is_complete__ 0B __synthesis_is_complete__ 0B __synthesis_is_complete__ 0B libxil.a 1.12MB libxil.a 1.11MB libfreertos.a 264KB runme.bat 229B runme.bat 229B runme.bat 229B runme.bat 229B runme.bat 229B runme.bat 229B runme.bat 229B bd_b43a.bd 52KB bd_b43a.bd 52KB top.bd 25KB top_wrapper.bit 1.99MB top_wrapper.bit 1.99MB bd_b43a.bxml 7KB top.bxml 4KB ps7_init.c 515KB ps7_init.c 515KB ps7_init_gpl.c 514KB ps7_init_gpl.c 514KB tasks.c 163KB queue.c 91KB xadcps.c 54KB xadcps.c 54KB xdmaps.c 52KB xdmaps.c 52KB xil_cache.c 46KB xil_cache.c 46KB timers.c 39KB xscugic.c 37KB xscugic.c 37KB xdevcfg.c 29KB xdevcfg.c 29KB xgpiops.c 28KB xgpiops.c 28KB xgpiops_intr.c 27KB xgpiops_intr.c 27KB port.c 26KB event_groups.c 25KB xuartps_options.c 24KB xuartps_options.c 24KB xuartps.c 22KB xuartps.c 22KB xscugic_hw.c 21KB xscugic_hw.c 21KB xil_testmem.c 20KB xil_testmem.c 20KB xil_misc_psreset_api.c 16KB xil_misc_psreset_api.c 16KB xuartps_intr.c 14KB xuartps_intr.c 14KB heap_4.c 14KB xgpiops_hw.c 12KB xgpiops_hw.c 12KB xil_exception.c 12KB xil_exception.c 12KB _profile_timer_hw.c 12KB _profile_timer_hw.c 12KB xil_printf.c 12KB xil_printf.c 12KB xil_testcache.c 10KB xil_testcache.c 10KB portZynq7000.c 9KB xdevcfg_intr.c 9KB xdevcfg_intr.c 9KB xil_testio.c 8KB xil_testio.c 8KB xscutimer.c 8KB xscutimer.c 8KB list.c 8KB xadcps_intr.c 8KB xadcps_intr.c 8KB xpm_counter.c 8KB xpm_counter.c 8KB xil_mmu.c 8KB xil_mmu.c 8KB xscugic_intr.c 7KB xscugic_intr.c 7KB xscuwdt.c 6KB xscuwdt.c 6KB vectors.c 6KB vectors.c 6KB xuartps_selftest.c 6KB xuartps_selftest.c 6KB xil_sleeptimer.c 6KB xil_sleeptimer.c 6KB xuartps_hw.c 6KB xuartps_hw.c 6KB xcoresightpsdcc.c 5KB xcoresightpsdcc.c 5KB xplatform_info.c 5KB xplatform_info.c 5KB xl2cc_counter.c 5KB共 1432 条
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