UM10562 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1 — 13 September 2012 4 of 942
NXP Semiconductors
UM10562
Chapter 1: Introductory information
1.2 Features
Refer to Section 1.4 for details of features for specific part numbers.
• Functional replacement for LPC23xx and 24xx family devices.
• ARM Cortex-M4 processor, running at frequencies of up to 120 MHz. The Cortex-M4
executes the Thumb®-2 instruction set for optimal performance and code size,
including hardware division, single cycle multiply, and bit-field manipulation. A
Memory Protection Unit (MPU) supporting eight regions is included.
• Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
• Cortex-M4 Floating Point Unit (FPU), supporting single-precision floating-point
computation functionality in compliance with the ANSI/IEEE Standard 754-2008. The
FPU provides add, subtract, multiply, divide, multiply and accumulate, and square root
operations. It also performs a variety of conversions between fixed-point,
floating-point, and integer data formats. The FPU is not available on LPC4074
devices.
• Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. The combination of an enhanced flash
memory accelerator and location of the flash memory on the CPU local code/data bus
provides high code performance from flash.
• Up to 96 kB on-chip SRAM includes:
– Up to 64 kB of Main SRAM on the CPU code/data bus for high-performance CPU
access.
– Up to two 16 kB SRAM blocks with separate access paths for higher throughput.
These SRAM blocks may be used for Ethernet, USB, LCD, and DMA memory, as
well as for general purpose instruction and data storage.
– Up to 4,032 bytes of on-chip EEPROM.
• External Memory Controller provides support for asynchronous static memory devices
such as RAM, ROM and Flash up to 64 MB, as well as dynamic memories such as
Single Data Rate SDRAM.
• Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I
2
S, UART, SD/MMC, CRC engine,
Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals,
GPIO, and for memory-to-memory transfers.
• Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, LCD
controller, and the USB interface. This interconnect provides communication with no
arbitration delays unless two masters attempt to access the same slave at the same
time.
• Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
• LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistor (TFT) displays. The LCD controller is not available on LPC407x devices.
– Dedicated DMA controller.
– Selectable display resolution (up to 1024 × 768 pixels).
