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FPGA项目-最简单的四位进制乘法器（Artix-7） 测试板材： Artix-7 xc7a100tcsg324
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2024-03-17
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FPGA项目-最简单的四位进制乘法器（Artix-7）
测试板材： Artix-7 xc7a100tcsg324 （157个子文件） 
__synthesis_is_complete__ 0B elaborate.bat 899B compile.bat 822B simulate.bat 780B runme.bat 229B runme.bat 229B top.bit 3.65MB xsim_1.c 6KB xsim.dbg 11KB top_routed.dcp 189KB top_placed.dcp 172KB top_opt.dcp 147KB top.dcp 33KB
xsimk.exe 83KB
usage_statistics_webtalk.html 31KB usage_statistics_ext_xsim.html 3KB .xsim_webtallk.info 64B xsimSettings.ini 1KB xsim.ini 40B webtalk.jou 929B webtalk_42280.backup.jou 929B vivado.jou 733B vivado.jou 728B ISEWrap.js 7KB ISEWrap.js 7KB rundef.js 1KB rundef.js 1KB hs_err_pid42036.log 66KB runme.log 26KB runme.log 21KB elaborate.log 2KB webtalk_42280.backup.log 998B webtalk.log 998B xvlog.log 861B compile.log 861B xsimkernel.log 315B simulate.log 50B xsimcrash.log 0B mult_4x4.lpr 290B xsim.mem 5KB xsim_0.win64.obj 26KB xsim_1.win64.obj 4KB vivado.pb 36KB route_design.pb 12KB place_design.pb 12KB opt_design.pb 11KB write_bitstream.pb 6KB xelab.pb 3KB init_design.pb 2KB xvlog.pb 2KB top_power_summary_routed.pb 722B top_utilization_placed.pb 242B top_utilization_synth.pb 242B vivado.pb 149B top_timing_summary_routed.pb 52B top_methodology_drc_routed.pb 52B top_route_status.pb 44B top_drc_routed.pb 37B top_drc_opted.pb 37B top_bus_skew_routed.pb 30B tb_vlog.prj 314B xsim.reloc 2KB xil_defaultlib.rlx 833B xsim.rlx 747B top_io_placed.rpt 97KB top_clock_utilization_routed.rpt 12KB top_utilization_placed.rpt 9KB top_power_routed.rpt 8KB top_timing_summary_routed.rpt 7KB top_methodology_drc_routed.rpt 7KB top_utilization_synth.rpt 7KB top_drc_routed.rpt 4KB top_drc_opted.rpt 4KB top_control_sets_placed.rpt 4KB top_bus_skew_routed.rpt 830B top_route_status.rpt 588B top_power_routed.rpx 52KB top_methodology_drc_routed.rpx 9KB top_timing_summary_routed.rpx 8KB top_drc_routed.rpx 5KB top_drc_opted.rpx 5KB top_bus_skew_routed.rpx 983B .route_design.begin.rst 180B .opt_design.begin.rst 180B .write_bitstream.begin.rst 180B .place_design.begin.rst 180B .init_design.begin.rst 180B .vivado.begin.rst 179B .vivado.begin.rst 178B .vivado.end.rst 0B .init_design.end.rst 0B .Vivado_Implementation.queue.rst 0B .write_bitstream.end.rst 0B .route_design.end.rst 0B .opt_design.end.rst 0B .place_design.end.rst 0B .vivado.end.rst 0B .Vivado_Synthesis.queue.rst 0B xsim.rtti 190B mult.sdb 5KB共 157 条
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