################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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cyusb3014_slavefifo模式XILINX Artix7 XC7A35T FPGA逻辑verilog例程源码:
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cyusb3014-slavefifo模式XILINX Artix7 XC7A35T FPGA逻辑verilog例程源码 (336个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
slaveFIFO2b_fpga_top.bit 2.09MB
cyfxslfifosync.c 33KB
cyfxtx.c 15KB
cyfxslfifousbdscr.c 14KB
.cproject 53KB
waveform.csv 64KB
waveform.csv 64KB
waveform.csv 234B
waveform.csv 61B
waveform.csv 50B
GPIFII_Designer_sync_SlaveFIFO.cyfx 2KB
cyfxslfifosync.d 5KB
cyfxslfifosync.d 5KB
cyfxtx.d 2KB
cyfxtx.d 1KB
cyfxslfifousbdscr.d 1KB
cyfxslfifousbdscr.d 1KB
cyfx_gcc_startup.d 62B
cyfx_gcc_startup.d 43B
xsim.dbg 2KB
xsim.dbg 2KB
xsim.dbg 2KB
xsim.dbg 744B
xsim.dbg 744B
xsim.dbg 744B
xsim.dbg 632B
slaveFIFO2b_fpga_top_routed.dcp 3.83MB
slaveFIFO2b_fpga_top_placed.dcp 3.38MB
slaveFIFO2b_fpga_top_opt.dcp 2.41MB
slaveFIFO2b_fpga_top.dcp 128KB
clk_wiz_0.dcp 12KB
clk_wiz_0.dcp 12KB
clk_wiz_0.dcp 9KB
waveform.dmp 116KB
waveform.dmp 116KB
waveform.dmp 491B
waveform.dmp 491B
waveform.dmp 491B
compile.do 623B
compile.do 599B
compile.do 558B
compile.do 548B
simulate.do 311B
simulate.do 306B
simulate.do 306B
simulate.do 195B
elaborate.do 183B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
SlaveFifoSync.elf 2.12MB
SlaveFifoSync.elf 1.21MB
run.f 410B
run.f 394B
cyfxgpif2config.h 7KB
cyfxgpif2config.h 7KB
cyfxslfifosync.h 4KB
usage_statistics_webtalk.html 36KB
usage_statistics_ext_labtool.html 3KB
hw_ila_data_1.ila 4KB
hw_ila_data_2.ila 3KB
SlaveFifoSync.img 155KB
SF_streamOUT.img 130KB
SF_streamIN.img 130KB
SF_loopback.img 130KB
SF_shrt_ZLP.img 130KB
SF_streamOUT.img 106KB
SF_streamIN.img 106KB
SF_loopback.img 106KB
SF_shrt_ZLP.img 106KB
.xsim_webtallk.info 59B
xsim.ini 22KB
version.ini 26B
vivado.jou 16KB
vivado.jou 950B
vivado.jou 946B
vivado.jou 931B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
.lock 0B
.clk_wiz_0.xcix.lock 0B
runme.log 77KB
runme.log 51KB
vivado.log 42KB
runme.log 23KB
ip_upgrade.log 11KB
.log 6KB
labtool_webtalk.log 768B
project_led.lpr 343B
共 336 条
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