毕业设计外文翻译--89C51单片机.docx

The Description of AT89S51

1 General Description

The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with

4K bytes of In-System Programmable Flash memory. The device is manufactured using

Atmel’s high-density nonvolatile memory technology and is compatible with the

The AT89S51 provides the following standard features: 4K bytes of Flash, 128

bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit

timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port,

on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static

logic for operation down to zero frequency and supports two software selectable power

saving modes.

The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port,

and interrupt system to continue functioning. The Power-down mode saves the RAM

contents but freezes the oscillator, disabling all other chip functions until the next

external interrupt or hardware reset.

outputs the code bytes during program verification. External pull-ups are required during

program verification.

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output

buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are

pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that

are externally being pulled low will source current (I

IL

) because of the internal pull-ups.

Port 1 also receives the low-order address bytes during Flash programming and

verification.

Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output

@ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s.

During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2

emits the contents of the P2 Special Function Register. Port 2 also receives the

high-order address bits and some control signals during Flash programming and

verification.

Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output

buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are

pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that

are externally being pulled low will source current (I

IL

the functions of various special features of the AT89S51, as shown in the following

table.

3 Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up

to 64K bytes each of external Program and Data Memory can be addressed.

3.1 Program Memory

If the EA pin is connected to GND, all program fetches are directed to external

memory. On the AT89S51, if EA is connected to V

0000H through FFFH are directed to internal memory and fetches to addresses 1000H

through FFFFH are directed to external memory.

3.2 Data Memory

Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To

enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST