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基于FPGA的简易数字时钟设计
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2021-11-11
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基于FPGA的简易数字时钟设计 （142个子文件） 
__synthesis_is_complete__ 0B elaborate.bat 1KB simulate.bat 912B compile.bat 834B runme.bat 229B runme.bat 229B xsim_1.c 5KB xsim.dbg 8KB clock_routed.dcp 403KB clock_placed.dcp 396KB clock_opt.dcp 17KB clock.dcp 16KB
xsimk.exe 80KB
usage_statistics_ext_xsim.html 4KB .xsim_webtallk.info 65B xsimSettings.ini 1KB xsim.ini 40B webtalk_12644.backup.jou 766B webtalk_17684.backup.jou 766B webtalk.jou 766B webtalk_11072.backup.jou 766B webtalk_5872.backup.jou 765B webtalk_5064.backup.jou 765B vivado.jou 635B vivado.jou 630B ISEWrap.js 8KB ISEWrap.js 8KB rundef.js 1KB rundef.js 1KB runme.log 24KB runme.log 14KB webtalk_11072.backup.log 1KB webtalk.log 1KB webtalk_17684.backup.log 1KB webtalk_12644.backup.log 1KB webtalk_5064.backup.log 1KB webtalk_5872.backup.log 944B elaborate.log 735B compile.log 330B xvlog.log 330B xsimcrash.log 252B xsimkernel.log 224B simulate.log 0B clock.lpr 290B xsim.mem 4KB xsim_0.win64.obj 22KB xsim_1.win64.obj 4KB vivado.pb 23KB place_design.pb 12KB route_design.pb 12KB opt_design.pb 10KB init_design.pb 2KB xelab.pb 1KB clock_power_summary_routed.pb 722B xvlog.pb 630B clock_utilization_synth.pb 289B clock_utilization_placed.pb 289B vivado.pb 149B clock_methodology_drc_routed.pb 52B clock_timing_summary_routed.pb 52B clock_route_status.pb 43B clock_drc_opted.pb 37B clock_drc_routed.pb 37B clock_bus_skew_routed.pb 30B clock_tb_vlog.prj 277B xsim.reloc 2KB xsim.rlx 770B xil_defaultlib.rlx 335B clock_io_placed.rpt 350KB clock_clock_utilization_routed.rpt 12KB clock_utilization_placed.rpt 9KB clock_power_routed.rpt 8KB clock_timing_summary_routed.rpt 7KB clock_utilization_synth.rpt 7KB clock_methodology_drc_routed.rpt 5KB clock_drc_routed.rpt 5KB clock_drc_opted.rpt 5KB clock_control_sets_placed.rpt 4KB clock_bus_skew_routed.rpt 852B clock_route_status.rpt 588B clock_power_routed.rpx 23KB clock_timing_summary_routed.rpx 7KB clock_drc_routed.rpx 6KB clock_drc_opted.rpx 6KB clock_methodology_drc_routed.rpx 6KB clock_bus_skew_routed.rpx 1014B .vivado.begin.rst 219B .vivado.begin.rst 219B .init_design.begin.rst 182B .route_design.begin.rst 182B .place_design.begin.rst 182B .opt_design.begin.rst 182B .vivado.end.rst 0B .init_design.end.rst 0B .Vivado_Synthesis.queue.rst 0B .Vivado_Implementation.queue.rst 0B .route_design.end.rst 0B .place_design.end.rst 0B .opt_design.end.rst 0B .vivado.end.rst 0B共 142 条
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