XC7K325T驱动程序，Verilog HDL实现。 项目代码可顺利编译运行~~
XC7K325T实现驱动OV5640摄像头采集图像Sobel边缘检测处理【Verilog HDL驱动】 （732个子文件） 
__synthesis_is_complete__ 0B __synthesis_is_complete__ 0B __synthesis_is_complete__ 0B __synthesis_is_complete__ 0B __synthesis_is_complete__ 0B xsim_run.bat 3KB xsim_run.bat 3KB runme.bat 305B runme.bat 305B runme.bat 305B runme.bat 305B runme.bat 305B runme.bat 305B ov5640_hdmi_sobel.bit 3.86MB ov5640_hdmi_sobel_routed.dcp 13.5MB ov5640_hdmi_sobel_placed.dcp 11.53MB ov5640_hdmi_sobel_physopt.dcp 11.46MB ov5640_hdmi_sobel_opt.dcp 8.84MB mig_7series_0.dcp 4.98MB mig_7series_0.dcp 4.93MB mig_7series_0.dcp 4.93MB wr_fifo.dcp 913KB rd_fifo.dcp 913KB wr_fifo.dcp 794KB wr_fifo.dcp 794KB rd_fifo.dcp 791KB wr_fifo.dcp 791KB rd_fifo.dcp 791KB rd_fifo.dcp 791KB ov5640_hdmi_sobel.dcp 651KB cordic_0.dcp 178KB clk_wiz_0.dcp 13KB clk_wiz_0.dcp 13KB clk_wiz_0.dcp 13KB clk_wiz_0.dcp 13KB clk_wiz_0.dcp 13KB clk_wiz_0.dcp 11KB compile.do 9KB compile.do 9KB compile.do 9KB compile.do 9KB sim.do 7KB sim.do 7KB simulate.do 371B simulate.do 300B simulate.do 300B simulate.do 255B elaborate.do 217B simulate.do 117B wave.do 32B wave.do 32B simulate.do 11B xil_txt.in 1KB xil_txt.in 1KB xsim.ini 29KB vivado.jou 2KB vivado.jou 1005B vivado.jou 984B vivado.jou 979B vivado.jou 977B vivado.jou 963B vivado.jou 963B ISEWrap.js 8KB ISEWrap.js 8KB ISEWrap.js 8KB ISEWrap.js 8KB ISEWrap.js 8KB ISEWrap.js 8KB rundef.js 1KB rundef.js 1KB rundef.js 1KB rundef.js 1KB rundef.js 1KB rundef.js 1KB runme.log 235KB runme.log 109KB runme.log 96KB runme.log 47KB runme.log 20KB vivado.log 9KB runme.log 3KB summary.log 980B ov5640_hdmi_sobel.lpr 343B elab.opt 201B xil_txt.out 161B xil_txt.out 161B vivado.pb 355KB vivado.pb 93KB vivado.pb 73KB write_bitstream.pb 71KB vivado.pb 31KB place_design.pb 26KB route_design.pb 22KB phys_opt_design.pb 19KB opt_design.pb 13KB init_design.pb 9KB vivado.pb 3KB ov5640_hdmi_sobel_power_summary_routed.pb 867B vivado.pb 857B clk_wiz_0_utilization_synth.pb 289B共 732 条
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