/*****************************************************************************
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
* 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
* cacheable regions
* Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
* generated by the cpu driver, for enabling caches
* 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
* write-thru caches
* 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
* Updated the MMU table to mark OCM in high address space
* as inner cacheable and reserved space as Invalid
* 3.03a sdm 08/20/11 Changes to support FreeRTOS
* Updated the MMU table to mark upper half of the DDR as
* non-cacheable
* Setup supervisor and abort mode stacks
* Do not initialize/enable L2CC in case of AMP
* Initialize UART1 for 9600bps in case of AMP
* 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
* in case of AMP
* 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
* counters
* 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
* xparameters.h file for CR630532 - Xil_DCacheFlush()/
* Xil_DCacheFlushRange() functions in standalone BSP v3_02a
* for MicroBlaze will invalidate data in the cache instead
* of flushing it for writeback caches
* 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
* Remove redundant dsb/dmb instructions in cache maintenance
* APIs
* Remove redundant dsb in mcr instruction
* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
* 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
* driver tcl in xparameters.h. Update the gcc/translationtable.s
* for the QSPI complete address range - DT644567
* Removed profile directory for armcc compiler and changed
* profiling setting to false in standalone_v2_1_0.tcl file
* Deleting boot.S file after preprocessing for armcc compiler
* 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
* invalidate the caches before enabling back the MMU and
* D cache.
* 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
* xil_mmu.c. Now we invalidate UTLB, Branch predictor
* array, flush the D-cache before changing the attributes
* in translation table. The user need not call Xil_DisableMMU
* before calling Xil_SetTlbAttributes.
* 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
* sgd initialization is present. Changes for this were done in
* uart.c and xil-crt0.s.
* Made changes in xil_io.c to use volatile pointers.
* Made changes in xil_mmu.c to correct the function
* Xil_SetTlbAttributes.
* Changes are made xil-crt0.s to initialize the static
* C++ constructors.
* Changes are made in boot.s, to fix the TTBR settings,
* correct the L2 Cache Auxiliary register settings, L2 cache
* latency settings.
* 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
* sgd usleep.c to use global timer instead of CP15.
* Made changes in cortexa9/gcc/translation_table.s to map
* the peripheral devices as shareable device memory.
* Made changes in cortexa9/gcc/xil-crt0.s to initialize
* the global timer.
* Made changes in cortexa9/armcc/boot.S to initialize
* the global timer.
* Made changes in cortexa9/armcc/translation_table.s to
* map the peripheral devices as shareable device memory.
* Made changes in cortexa9/gcc/boot.S to optimize the
* L2 cache settings. Changes the section properties for
* ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
* and cortexa9/gcc/translation_table.S.
* Made changes in cortexa9/xil_cache.c to change the
* cache invalidation order.
* 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
* compilation/linking issues for C++ compiler.
* Made changes in mb_interface.h to remove compilation/
* linking issues for C++ compiler.
* Added macros for swapb and swaph microblaze instructions
* mb_interface.h
* Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
* for CortexA9.
* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
* 3.07a asa 08/31/12 Added xil_printf.h include
* 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
* Corrected L2 cache sequence disable sequence
* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
* 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
* irq/fiq handling.
* Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
* fixes the CR #692094.
* 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
* 3.10a srt 04/18/13 Implemented ARM Erratas.
* Cortex A9 Errata - 742230, 743622, 775420, 794073
* L2Cache PL310 Errata - 588369, 727915, 759370
* Please refer to file 'xil_errata.h' for errata
* description.
* 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
* cache APIs were corresponding to only Layer 1 cache
* memories. New APIs were now added and the existing cache
* related APIs were changed to provide a uniform interface
* to flush/invalidate/enable/disable the complete cache
* system which includes both L1 and L2 caches. The changes
* for these were done in:
* src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
* files.
* Four new files were added for supporting L2 cache. They are:
* microblaze_flush_cache_ext.S-> Flushes L2 cache
* microblaze_flush_cache_ext_range.S -> Flushes a range of
* memory in L2 cache.
* microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
* microblaze_invalidate_cache_ext_range -> Invalidates a
* range of memory in L2 cache.
* These changes are done to implement PR #697214.
* 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
* fix the CR #706464. L2 cache disabling happens independent
* of L1 data cache disable operation. Changes are done in the
* same file in cache handling APIs to do a L2 cache sync
* (poll reg7_?cache_?sync). This fixes CR #700542.
* 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
* interrupts for ARM. These are done to fix the CR#699680.
* 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
* sync operation. This fixes the CR# 716781.
* 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support
* for armcc toolchain.
* Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
* fix issues related to NEON context saving. The assembly
* routines for IRQ and FIQ handling are modified.
* Deprecated the older BSP (3.10a).
* 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
* various potential issues. Made changes i
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FPGA MPSoC_XCZU2EG实现QSPI Flash读写数据(VITIS实现).zip (2000个子文件)
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psu_init_gpl.c 641KB
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xfsbl_ddr_init.c 214KB
xilskey_eps_zynqmp.c 102KB
xilfpga_pcap.c 75KB
pm_clock.c 70KB
xsysmonpsu.c 69KB
xsysmonpsu.c 69KB
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