REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
REM
vivado -log top_key_beep.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_key_beep.tcl -notrace
FPGA XC7A200T实现按键控制蜂鸣器（Verilog HDL实现）.zip
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FPGA XC7A200T实现按键控制蜂鸣器（Verilog HDL实现）.zip （99个子文件） 
FPGA XC7A200T实现按键控制蜂鸣器（Verilog HDL实现） top_key_beep.ip_user_files top_key_beep.runs impl_1 
top_key_beep_drc_opted.rpt 2KB runme.bat 229B .vivado.begin.rst 220B .route_design.begin.rst 182B top_key_beep.bit 9.28MB top_key_beep_control_sets_placed.rpt 4KB top_key_beep_drc_routed.pb 37B top_key_beep_route_status.rpt 588B top_key_beep_power_summary_routed.pb 722B init_design.pb 3KB .vivado.end.rst 0B .init_design.end.rst 0B runme.log 27KB top_key_beep_drc_routed.rpt 2KB rundef.js 1KB .opt_design.begin.rst 182B .write_bitstream.begin.rst 182B
htr.txt 409B top_key_beep_timing_summary_routed.rpt 7KB .Vivado_Implementation.queue.rst 0B top_key_beep.tcl 6KB top_key_beep_bus_skew_routed.rpt 920B top_key_beep_power_routed.rpt 8KB .Xil .write_bitstream.end.rst 0B
usage_statistics_webtalk.html 31KB write_bitstream.pb 4KB top_key_beep_methodology_drc_routed.rpx 6KB top_key_beep_bus_skew_routed.rpx 1KB top_key_beep.vdi 27KB route_design.pb 12KB top_key_beep_utilization_placed.rpt 9KB top_key_beep_routed.dcp 151KB top_key_beep_power_routed.rpx 24KB .place_design.begin.rst 182B .route_design.end.rst 0B project.wdf 4KB top_key_beep_methodology_drc_routed.pb 52B usage_statistics_webtalk.xml 44KB top_key_beep_clock_utilization_routed.rpt 12KB top_key_beep_drc_opted.pb 37B top_key_beep_utilization_placed.pb 276B top_key_beep_drc_routed.rpx 2KB top_key_beep_timing_summary_routed.pb 52B .opt_design.end.rst 0B vivado.jou 736B vivado.pb 149B top_key_beep_bus_skew_routed.pb 30B top_key_beep_timing_summary_routed.rpx 7KB top_key_beep_placed.dcp 144KB opt_design.pb 11KB .init_design.begin.rst 182B top_key_beep_opt.dcp 129KB top_key_beep_io_placed.rpt 144KB gen_run.xml 8KB runme.sh 1KB .place_design.end.rst 0B place_design.pb 12KB ISEWrap.js 8KB top_key_beep_drc_opted.rpx 2KB ISEWrap.sh 2KB top_key_beep_route_status.pb 43B top_key_beep_methodology_drc_routed.rpt 5KB .jobs vrs_config_1.xml 607B vrs_config_3.xml 677B vrs_config_4.xml 591B vrs_config_2.xml 613B synth_1 runme.bat 229B .vivado.begin.rst 221B .vivado.end.rst 0B runme.log 19KB rundef.js 1KB htr.txt 401B top_key_beep.tcl 3KB .Xil top_key_beep_propImpl.xdc 893B top_key_beep_utilization_synth.rpt 7KB top_key_beep.vds 19KB top_key_beep_utilization_synth.pb 276B __synthesis_is_complete__ 0B .Vivado_Synthesis.queue.rst 0B vivado.jou 731B vivado.pb 31KB gen_run.xml 3KB top_key_beep.dcp 18KB runme.sh 1KB ISEWrap.js 8KB ISEWrap.sh 2KB top_key_beep.cache compile_simlib riviera vcs modelsim xcelium ies activehdl questa ip 2019.2 wt java_command_handlers.wdf 2KB webtalk_pa.xml 8KB project.wpc 122B gui_handlers.wdf 9KB synthesis_details.wdf 100B synthesis.wdf 5KB .Xil top_key_beep.xpr 10KB top_key_beep.sim top_key_beep.hw hw_1 hw.xml 2KB wave top_key_beep.lpr 343B top_key_beep.srcs constrs_1 new key_beep.xdc 301B sources_1 new beep_control.v 2KB top_key_beep.v 2KB key_debounce.v 3KB资源评论
