FPGAXC7A200T实现HDMI方块移动（VerilogHDL实现）.zip资源-CSDN文库

共127个文件

rst：18个

pb：17个

rpt：12个

版权申诉

FPGA

XC7A200T

VerilogHDL

驱动程序

117 浏览量 2023-04-04 17:11:26 上传评论收藏 1.34MB ZIP 举报

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FPGA XC7A200T实现HDMI方块移动（Verilog HDL实现）.zip （127个子文件）

__synthesis_is_complete__ 0B

runme.bat 229B

hdmi_block_move_top.bit 9.28MB

hdmi_block_move_top_routed.dcp 294KB

hdmi_block_move_top_physopt.dcp 266KB

hdmi_block_move_top_placed.dcp 264KB

hdmi_block_move_top_opt.dcp 201KB

hdmi_block_move_top.dcp 74KB

clk_wiz_0.dcp 10KB

usage_statistics_webtalk.html 39KB

vivado.jou 809B

vivado.jou 804B

ISEWrap.js 8KB

rundef.js 1KB

runme.log 46KB

runme.log 34KB

hdmi_block_move_top.lpr 343B

vivado.pb 77KB

place_design.pb 18KB

route_design.pb 15KB

opt_design.pb 11KB

init_design.pb 5KB

write_bitstream.pb 4KB

phys_opt_design.pb 2KB

hdmi_block_move_top_power_summary_routed.pb 728B

hdmi_block_move_top_utilization_placed.pb 276B

hdmi_block_move_top_utilization_synth.pb 276B

vivado.pb 149B

hdmi_block_move_top_timing_summary_routed.pb 109B

hdmi_block_move_top_methodology_drc_routed.pb 52B

hdmi_block_move_top_route_status.pb 44B

hdmi_block_move_top_drc_opted.pb 37B

hdmi_block_move_top_drc_routed.pb 37B

hdmi_block_move_top_bus_skew_routed.pb 30B

hdmi_block_move_top_timing_summary_routed.rpt 217KB

hdmi_block_move_top_io_placed.rpt 146KB

hdmi_block_move_top_clock_utilization_routed.rpt 19KB

hdmi_block_move_top_utilization_placed.rpt 9KB

hdmi_block_move_top_power_routed.rpt 8KB

hdmi_block_move_top_utilization_synth.rpt 7KB

hdmi_block_move_top_control_sets_placed.rpt 5KB

hdmi_block_move_top_drc_routed.rpt 2KB

hdmi_block_move_top_drc_opted.rpt 2KB

hdmi_block_move_top_methodology_drc_routed.rpt 1KB

hdmi_block_move_top_bus_skew_routed.rpt 990B

hdmi_block_move_top_route_status.rpt 588B

hdmi_block_move_top_timing_summary_routed.rpx 191KB

hdmi_block_move_top_power_routed.rpx 113KB

hdmi_block_move_top_drc_routed.rpx 2KB

hdmi_block_move_top_drc_opted.rpx 2KB

hdmi_block_move_top_bus_skew_routed.rpx 1KB

hdmi_block_move_top_methodology_drc_routed.rpx 138B

.vivado.begin.rst 220B

.route_design.begin.rst 182B

.write_bitstream.begin.rst 182B

.phys_opt_design.begin.rst 182B

.opt_design.begin.rst 182B

.place_design.begin.rst 182B

.init_design.begin.rst 182B

.init_design.end.rst 0B

.vivado.end.rst 0B

.Vivado_Implementation.queue.rst 0B

.write_bitstream.end.rst 0B

.place_design.end.rst 0B

.opt_design.end.rst 0B

.route_design.end.rst 0B

.phys_opt_design.end.rst 0B

.vivado.end.rst 0B

.Vivado_Synthesis.queue.rst 0B

ISEWrap.sh 2KB

runme.sh 1KB

hdmi_block_move_top.tcl 7KB

hdmi_block_move_top.tcl 4KB

htr.txt 423B

htr.txt 415B

README.txt 130B

clk_wiz_0_sim_netlist.v 7KB

clk_wiz_0_clk_wiz.v 7KB

rgb_display.v 5KB

dvi_encoder.v 5KB

serializer_10_to_1.v 5KB

dvi_transmitter_top.v 5KB

clk_wiz_0.v 4KB

rgb_driver.v 4KB

hdmi_block_move_top.v 3KB

asyn_rst_syn.v 2KB

clk_wiz_0_stub.v 1KB

hdmi_block_move_top.vdi 34KB

hdmi_block_move_top.vds 46KB

clk_wiz_0.veo 4KB

mmcm_pll_drp_func_us_plus_mmcm.vh 31KB

mmcm_pll_drp_func_7s_mmcm.vh 24KB

mmcm_pll_drp_func_us_mmcm.vh 24KB

共 127 条

The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

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