################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA XC7A200T实现IP核之FIFO驱动(Verilog HDL实现).zip
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FPGA XC7A200T实现IP核之FIFO驱动(Verilog HDL实现).zip (366个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
ip_fifo.bit 9.28MB
ip_fifo_routed.dcp 2.09MB
ip_fifo_physopt.dcp 1.85MB
ip_fifo_placed.dcp 1.85MB
ip_fifo_opt.dcp 1.47MB
ila_0.dcp 697KB
ila_0.dcp 697KB
ila_0.dcp 695KB
dbg_hub.dcp 350KB
fifo_generator_0.dcp 104KB
fifo_generator_0.dcp 104KB
fifo_generator_0.dcp 103KB
ip_fifo.dcp 18KB
compile.do 1KB
compile.do 1015B
compile.do 964B
compile.do 950B
compile.do 733B
compile.do 709B
compile.do 668B
compile.do 658B
simulate.do 353B
simulate.do 353B
simulate.do 351B
simulate.do 303B
simulate.do 294B
simulate.do 294B
elaborate.do 223B
simulate.do 209B
simulate.do 187B
elaborate.do 175B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
run.f 810B
run.f 782B
run.f 444B
run.f 428B
usage_statistics_webtalk.html 160KB
usage_statistics_ext_labtool.html 3KB
hw_ila_data_1.ila 35KB
.xsim_webtallk.info 59B
xsim.ini 26KB
xsim.ini 26KB
vivado.jou 767B
vivado.jou 691B
vivado.jou 686B
vivado.jou 681B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 120KB
runme.log 46KB
runme.log 42KB
runme.log 25KB
labtool_webtalk.log 476B
ip_fifo.lpr 343B
ip_fifo.ltx 13KB
debug_nets.ltx 13KB
elab.opt 228B
elab.opt 180B
vivado.pb 191KB
vivado.pb 76KB
vivado.pb 41KB
place_design.pb 18KB
route_design.pb 15KB
opt_design.pb 15KB
write_bitstream.pb 10KB
init_design.pb 8KB
phys_opt_design.pb 2KB
messagePromote.pb 2KB
ip_fifo_power_summary_routed.pb 728B
ila_0_utilization_synth.pb 276B
ip_fifo_utilization_placed.pb 276B
ip_fifo_utilization_synth.pb 276B
fifo_generator_0_utilization_synth.pb 276B
vivado.pb 149B
ip_fifo_timing_summary_routed.pb 109B
ip_fifo_drc_routed.pb 75B
ip_fifo_methodology_drc_routed.pb 52B
ip_fifo_route_status.pb 44B
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