################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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ZYNQ 7010实现IP_FIFO驱动(FPGA驱动).zip (374个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
ip_fifo.bit 1.99MB
ip_fifo_routed.dcp 2.25MB
ip_fifo_placed.dcp 1.99MB
ip_fifo_opt.dcp 1.42MB
ila_0.dcp 730KB
ila_0.dcp 730KB
ila_0.dcp 728KB
u_ila_0.dcp 727KB
u_ila_0.dcp 720KB
dbg_hub.dcp 347KB
fifo_generator_0.dcp 101KB
fifo_generator_0.dcp 101KB
fifo_generator_0.dcp 100KB
ip_fifo.dcp 16KB
compile.do 1KB
compile.do 1KB
compile.do 975B
compile.do 961B
compile.do 783B
compile.do 759B
compile.do 718B
compile.do 708B
simulate.do 353B
simulate.do 353B
simulate.do 351B
simulate.do 303B
simulate.do 294B
simulate.do 294B
elaborate.do 223B
simulate.do 209B
simulate.do 187B
elaborate.do 175B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
run.f 821B
run.f 793B
run.f 494B
run.f 478B
usage_statistics_webtalk.html 161KB
hw_ila_data_1.ila 63KB
xsim.ini 22KB
xsim.ini 22KB
vivado.jou 776B
vivado.jou 675B
vivado.jou 670B
vivado.jou 665B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 138KB
runme.log 46KB
runme.log 39KB
runme.log 26KB
ip_fifo.lpr 343B
ip_fifo.ltx 14KB
debug_nets.ltx 14KB
elab.opt 228B
elab.opt 180B
vivado.pb 224KB
vivado.pb 76KB
vivado.pb 43KB
place_design.pb 17KB
route_design.pb 16KB
opt_design.pb 14KB
write_bitstream.pb 9KB
init_design.pb 8KB
messagePromote.pb 2KB
ip_fifo_power_summary_routed.pb 728B
ip_fifo_utilization_placed.pb 224B
ila_0_utilization_synth.pb 224B
ip_fifo_utilization_synth.pb 224B
fifo_generator_0_utilization_synth.pb 224B
vivado.pb 149B
ip_fifo_timing_summary_routed.pb 109B
ip_fifo_drc_routed.pb 75B
ip_fifo_methodology_drc_routed.pb 52B
ip_fifo_route_status.pb 44B
ip_fifo_drc_opted.pb 37B
ip_fifo_bus_skew_routed.pb 36B
vlog.prj 200B
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